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This page explains the Intel® FPGA development flow and introduces information that we would like you to refer to in each development phase.
| First of all, what is an FPGA? I want to use FPGA, but I don't know where to start! If so, this article is a must-see! ▶ FPGA is a magic box! <Honto no Honto Introduction> ▶ Part 1. Creating an environment to start FPGA development ▶ Part 2. What to prepare to start FPGA development ▶ Part 3. Necessary knowledge to start FPGA development ▶ Part 4. Flow of FPGA development ▶ Part 5. Introduction of useful content |
| Use the Intel® Quartus® Prime design software to develop for Intel® FPGAs. Anyone who wants to easily understand the basic operation of Quartus® Prime can learn it in this tutorial. ▶Quartus Prime Simple Tutorial The popular hands-on seminar is now available online! You can study at your own pace anytime, anywhere. ▶"Intel® Quartus® Prime Introductory Trial" released as a video! ▶"Nios® II Introductory Trial" is released as a video! ▶"SoC Startup Trial" is now open to the public! ▶"Intel® HLS Introductory Edition Trial" is now open to the public! |
Intel® FPGA Development Flow Diagram
Intel® FPGA is developed according to the flow shown in the diagram below. Click on the appropriate number to jump to each development phase.
(Click the appropriate number to jump to each development phase.)
1. Preparation
Download / Install / License setup
2. Examination of functional specifications
FPGA selection / configuration / power supply & power consumption estimation / board simulation
3. Logic circuit design
IP Information / Nios® II Information / SoC FPGA Information / OpenCL™ Information
Information on High Level Synthesis (HLS) / New to HDL design
4. Logical simulation
5. Constraint setting
6. Compile
7. Timing Verification
8. Programming
9. Actual equipment verification
10. Mass production
1. Preparation
Confirmation of correspondence status
Before proceeding with FPGA / CPLD design and development, let's find out what development environment you should prepare.
| The development software to be used differs depending on the FPGA / CPLD function to be developed and the device to be adopted. By the way, development software is sometimes called a "tool". Check in advance the OS of the PC where the tool will be installed and the amount of memory to be installed. <Support table> ▶ Quartus® Prime - Supported Windows® OS / Operating System Support (external site: Intel) ▶ Quartus® Prime - Supported Devices Correspondence Table |
| The memory capacity to be installed in the PC varies depending on the FPGA/CPLD to be developed. Details are in the release notes. (Search for Memory Recommendations in the release notes to find it.) <Release Notes> ▶ Quartus® Prime Pro Edition Release Notes < PDF > (external site: Intel) ▶ Quartus® Prime Standard Edition Release Notes < PDF > (external site: Intel) |
| Quartus® Prime has a paid version that requires a license and a free version that does not require a license. There are differences in supported devices and features. <Edition comparison> ▶ Quartus® Prime edition comparison (External site: Intel) |
download
To download the tool, please visit the page below.
▶ How to download Intel® Quartus® Prime software and Questa* - Intel® FPGA Edition
install
After downloading the installation file (installer) for the tool you want to install, the next step is installation.
See here for how to install each tool. (The Nios® II Software Build Tools (Nios® II SBT) are also required when using the Nios® II embedded processor, but the Nios® II SBT is automatically installed with the Quartus® Prime installation. )
▶ How to Install Intel® Quartus® Prime Software and Questa* - Intel® FPGA Edition
▶ How to install Intel® SoC FPGA Embedded Development Suite (SoC EDS) ver.20.1
▶ How to install the Intel® FPGA Software Development Kit (SDK) for OpenCL™
License settings
Once you have installed the tools, get and set up your license file. (The free-to-use Quartus® Prime Lite Edition can be used without obtaining and setting up a license file.)
To generate and update license files, sign in to the Intel website and use the dedicated site called Intel FPGA Self-Service License Center.
■ For sign-in, see the information below.
▶ How to sign up for an Intel® Account
▶ How to register for the Intel® FPGA Self-Service License Center
■ See below for information on how to obtain a license file.
▶ How to Get New Licenses for Intel® Quartus® Prime, IP and Questa* - Intel® FPGA Edition
▶ How to Obtain Intel® Quartus® Prime, IP and Questa* - Intel® FPGA Edition Licenses on Maintenance Renewal
▶ How to change the NIC ID (Host ID) associated with Intel® Quartus® Prime, IP and Questa* - Intel® FPGA Edition licenses
▶ How to issue (reissue) a license file for Intel® Quartus® Prime, IP and Questa* - Intel® FPGA Edition license with NIC ID assigned
▶ Questa* - How to obtain and configure the Intel® FPGA Starter Edition license file
▶ How to obtain a license file for the Nios® V processor IP
■ See the information below for setting up the license file.
Intel® FPGA licenses include FIXED license and FLOAT license There are two types of , but the setting method is different for each.
▶ Intel® Quartus® Prime Licensing Structure
▶ FIXED Licensing Instructions for Intel® Quartus® Prime, IP and Questa* - Intel® FPGA Edition
▶ Intel® Quartus® Prime, IP and Questa* - Intel® FPGA Edition FLOAT License Setup Instructions
▶ How to license Arm® Development Studio (DS) for Intel® SoC FPGA Edition
2. Examination of functional specifications
Consider the specifications of the functions to be implemented in FPGA / CPLD, and create block diagrams and specifications. By doing some paperwork and using Quartus® Prime to create a simple design (digital logic circuit), we thoroughly consider whether the functionality we want to implement is feasible.
In addition, in order to build a highly reliable logic circuit, it is important to learn the basics of design techniques, which are key points in RTL design of FPGA / CPLD. Before designing a logic circuit, we will introduce articles that FPGA / CPLD users must see. (Since it is easy to impose timing constraints, we recommend synchronous design especially for FPGA/CPLD. Regarding timing constraints, 5. Constraint setting Please refer to the. )
[A Must-See for Beginners in RTL Design] Series Articles
▶ [A must-see for RTL design beginners] Differences between synchronous and asynchronous design
▶ [Must-see for Beginners in RTL Design] Impact on the System when Inputting Asynchronous Signals
▶ [A Must-See for RTL Design Beginners] Effects of Hazard Signals on Systems
Now, I would like to introduce some materials and articles that I would like you to check in advance before proceeding with the specific consideration of FPGA.
FPGA selection
▶ Device selection: Product Specifications (External site: Intel)
▶ Device information (external site: Intel)
▶ Pin Information : Pin Connection Guidelines/ Pinout (external site: Intel)
▶ Various documents: User guides / Application notes (External site: Intel)
▶ Development kit information (external site: Intel)
configuration
▶ FPGA configuration
▶ Remote System Upgrade for Intel® FPGAs
▶ Active Serial Configuration Design & Debug Guidelines/FPGA Guidelines
Estimated Power Supply & Power Consumption
▶ FPGA Power Consumption Types and Calculation Methods
▶ Power & Thermal Design & Debug Guidelines/FPGA Guidelines
▶ Enpirion® related articles and resources
board simulation
▶ Substrate simulation (HyperLynx)
SI (signal quality)
PI (power quality)
Thermal
DRC (Design Rule Check)
3. Logic circuit design
Quartus® Prime supports design in hardware description languages (HDL) such as Verilog HDL, SystemVerilog, and VHDL, as well as schematic design. Quartus® Prime also allows mixing HDL and schematics in the same project.
To begin FPGA/CPLD development with Quartus® Prime, you must first create a project. After creating the project, we will create the design (digital logic circuit) in HDL and circuit diagrams, but if you want to design in circuit diagrams, please refer to the following materials.
Getting Started with Quartus® - Material for Beginners
▶ Quartus® Prime - How to create a project
▶ Quartus® Prime - Using the Schematic Editor
Quartus® Step-Up Guide - Material for Intermediate Users
▶ Quartus® Prime - Managing Projects
▶ Quartus® Prime - Device Migration
▶ Quartus® Prime - Using the Qsys System Integration Tool
* Qsys from Quartus Prime v17.1 Platform Designer has been renamed to
IP information
A variety of Intellectual Property (IP) is available for FPGAs from Intel and third parties. Please refer to those who use IP.
▶What is Intel® FPGA IP? (External site: Intel)
<PLL>
▶ Intel® FPGA PLL (← Please check this page to see which PLL version)
IOPLL edition / Altera PLL edition / ALTPLL edition
<External Memory Interface>
▶ Implement DDR memory controller on Intel® FPGA!
EMIF Design & Debug Guidelines/FPGA Guidelines
EMIF Layout Guidelines/FPGA Guidelines
DDR4 / DDR3
<PCI Express>
▶ PCI Express with Intel® FPGA
PCI Express Design & Debug Guidelines/FPGA Guidelines
Avalon-ST Edition / Avalon-MM Edition
<JESD204>
▶ JESD204B with Intel® FPGA
<HDMI>
▶ Easily display 4K video using HDMI 2.0 IP on Arria® 10 FPGA
Nios® II Information
If you want to implement the Nios® II processor in your design, please refer to these resources and articles.
▶ Nios® II Processor on Intel® FPGA
▶ Nios® II processor What is (External site: Intel)
SoC FPGA Information
For those using SoC FPGAs with Arm® cores, please refer to these resources and articles.
▶ Intel® FPGA SoC FPGA
▶ What is SoC FPGA? (External site: Intel)
OpenCL™ Information
If you are using the Intel® FPGA SDK for OpenCL™, please refer to these resources and articles.
▶What is Intel® FPGA SDK for OpenCL™? (External site: Intel)
Information about High Level Synthesis (HLS)
If you use the Intel HLS Compiler, here are some resources and articles to help you.
▶ HLS Compiler for Intel® FPGAs
▶ Intel HLS Compiler What is (External site: Intel)
New to HDL design
If you don't know how to write a hardware technology language (HDL), we have prepared content that you can learn with textbooks and exercises. If you learn this, you will be able to write a minimum description. Please take a look.
▶ Let's start! Verilog HDL <with exercises>
▶ Let's start! VHDL <with exercises>
4. Logical simulation
After the design is completed, the logic is verified by logic simulation. The simulation uses an RTL simulator such as ModelSim® - Intel® FPGA Edition, but the RTL simulator does not support schematics as Quartus® Prime does. For information on how to convert Quartus® Prime schematics to HDL, see Quartus® Prime - Using the Schematic Editor.
▶ Let's solve the function simulation of Intel® FPGA with NativeLink (for Standard Edition, Lite Edition)
▶ How to functionally simulate a design containing IP generated by Quartus® Prime Pro Edition on Questa* - Intel® FPGA Edition (for Pro Edition)
<Quartus® Beginner's Guide>-BeginnerA user materials for
▶ ModelSim® - Intel® FPGA Edition - How to RTL Simulation
ModelSim/Questa
For mid-range and higher FPGA development, we recommend Questa or ModelSim for their fast simulation speed.
▶ RTL Simulator & Debug Tool / Questa / ModelSim
5. Constraint setting
After the RTL simulation is finished, pinouts, device settings, and various constraints are applied. Before compiling, be sure to make the necessary settings and constraints.
<Quartus® Beginner's Guide>-BeginnerMaterials for users
▶ Quartus® Prime - How to set device options
▶ Quartus® Prime - How to make pin assignments
▶ Quartus® Prime - Timing Constraint Methods
<Quartus® Step-up Guide>- IntermediateA user materials for
▶ Quartus® Prime - How to set up the EDA tool
▶ Quartus® Prime - Constraint Method (Assignment Editor)
▶ Quartus® Prime - How to set common pin options
6. Compile
After completing various settings and constraints, compile. Full compilation performs logic synthesis, placement and routing, timing analysis, and creation of programming files. After compiling, be sure to check the compilation report.
<Quartus® Beginner's Guide>-BeginnerA user materials for
▶ Quartus® Prime - How to read the compilation report file
<Quartus® Step-up Guide>-Materials for intermediate users
7. Timing Verification
Check the timing analysis results at the same time as the compilation report. Timing analysis results on the compilation report are summary information only, use the TimeQuest Timing Analyzer to see detailed results.
<Quartus® Beginner's Guide>-BeginnerA user materials for
▶ Quartus® Prime - How to do Timing Analysis
< FPGA guidelines＞
▶ Timing & Implementation Design & Debug Guidelines/FPGA Guidelines
8. Programming
When you have come this far, you will be debugging the actual device, but when writing data to the FPGA / CPLD or configuration device, start the Quartus® Prime Programmer and use the Intel® FPGA download cable (USB-Blaster™ II or USB-Blaster™, etc.) to write to the device.
<Quartus® Beginner's Guide>-Beginneruser materials for
▶ Quartus® Prime - How to program your device
<Quartus® Step-up Guide>- Intermediateuser materials for
▶ Quartus® Prime - Convert Programming Files
<Those who want to know more>
▶ Programming to EPCQ device via FPGA (JIC programming)
▶ Install the USB-Blaster™ II driver
▶ Install the USB-Blaster™ driver
▶ Let's change the TCK frequency of USB-Blaster™ II
9. Actual equipment verification
If the evaluation board is powered on again and the data is successfully transferred from the configuration device to the FPGA, it enters the phase of verifying the operation of the FPGA.
Getting Started with Quartus® - Material for Beginners
▶ Using the Quartus® Prime - Signal Tap Logic Analyzer
<Those who want to know more>
▶ Let's try FPGA on-chip debugging "Signal Tap"
* SignalTap®II from Quartus Prime v17.1 Signal Tap has been renamed to
10. Mass production
Once the actual machine verification is completed, we can move to mass production.
Recommended information
Article/Material
<FPGA Guidelines>
Articles and resources related to FPGA guidelines
<Information on each FPGA family> (External site: Intel)
Agilex™
Stratix® 10 / Stratix® V / Stratix® IV
Arria® 10 / Arria® V / Arria® II
Cyclone® 10 / Cyclone® V / Cyclone® IV
MAX®10 / MAX®V / MAX®II
All FPGAs
* For documents, please click "Support" on each page.
FAQ
Seminar/Workshop
Quartus® Prime Introductory Trial Course <Free>
Nios® II Introductory Trial Course <Free>
SoC Startup Trial <Free>
Custom microcontroller design trial ~ Experience embedded design using MAX® 10 FPGA! ~ <Free>
Macnica original workshop
Experience at your own seat! Intel® FPGA Seminar In a Box
You can rent an evaluation board equipped with Intel® FPGA for two weeks, and you can easily experience the development flow of Intel® FPGA at your desk. We also provide practice manuals and practice data, so you can practice at your leisure.
Intel® Cyclone® 10 LP FPGA Seminar In a Box
Intel® SoC FPGA Seminar In a Box