Narrow down by specifying conditions
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Even though the device was designed and evaluated in the most natural way and shipped, if it was connected to other devices and operated, it would "malfunction sometimes" or "malfunction" in the heat of the summer. I sometimes hear people say, “I do.” Most of these causes are affected by timing, and are caused by input signals that are not synchronized with the system (asynchronous input signals) and hazards that occur on the circuit.
Therefore, in this article, I will explain the effects of input signals that are not synchronized with the system and how to solve them.
Learn more about how hazards affect your system.
[A Must-See for RTL Design Beginners] Effects of Hazard Signals on Systems
非同期入力
非同期入力の持つ意味
FPGA において、フリップフロップの入力信号とクロック信号との間には、安定して動作するための要求条件としてセットアップ・タイム（tSU）とホールド・タイム（tH）の規定があります。デジタル論理回路設計者はこれらの規定を厳守しなければなりません。この要求条件は、FPGA メーカーが提供する開発ソフトウェアの中に格納されています。図1にセットアップ・タイムとホールド・タイムの概念図を示します。
Violation of this setup/hold time specification can result in temporary instability called "metastability" or a state that differs from the system-defined state. This factor greatly affects the reliability of the system. When data is exchanged between different devices, it becomes an asynchronous system, and it is not possible to guarantee the setup time and hold time specifications between the received signal and the system clock. Synchronization of signals is required when sending and receiving signals between these devices, and metastability is likely to occur if this synchronization is not performed. (Metastability does not always occur. And even if it does occur, the time is usually on the order of ns, so it may not be a problem. However, although the probability is extremely low, metastable instability It may take a long time.)
メタステーブルとは
メタステーブルとは、本来規定されているクロックからの出力時間 tCO を超えても出力状態が安定しない状態を言います。安定するまでに必要な時間 tMET は、周囲条件やデバイスの製造技術に依存します。
レジスタの動作は、図2のようにボールが摩擦の無いひとつの山を移動する状態に例えて表すことができます。山の両側は安定した状態（High または Low）を表していて、山の頂上がメタステーブルの状態を表しています。
フリップフロップへの入力が規定のセットアップ・タイム tSU とホールド･タイム tHの最小値を満足している場合は、出力が一方の安定したステートからもう一方の安定したステートに（High から Low、または Low から High に）追加遅延無しで変化します。
On the other hand, if the data input to the flip-flop violates the stipulated setup time or hold time stipulations, the flip-flop will not be fully triggered and the output will be doubled within the stipulated time. It may not transition to one of the stable states immediately. This improper triggering can cause the output to glitch or temporarily metastable between a high and low state, causing the output to take longer to return to a stable state. Even under these conditions, the time from clock transition to output stabilization will increase.
Metastability does not necessarily make system performance unpredictable. As long as the flip-flop can be allowed to wait long enough to return to a stable state, this does not affect system performance and even if the output of the flip-flop is temporarily undefined, this A signal can return to a stable state before it is actually used. Therefore, by allowing additional time t MET for the signal to settle to a prespecified value, an unspecified signal can be avoided from propagating to other parts of the system. Masu.
System impact of metastability
As I said earlier, asynchronous inputs are bad for your system. Basically, once the flip-flops in the system become metastable, they become not only unstable, but in the worst case system hangs. There is no way to recover other than turning off the power. In this way, the state of metastability cannot be defined artificially from the system. Only the physical properties of the semiconductor can control the state. It's "God only knows".
A particularly vulnerable example is the case of identical clock systems. For example, sending and receiving signals between devices that operate on a 50MHz master oscillator. Even though they are nominally the same frequency, the two master oscillators have different frequency deviations and temperature coefficients, resulting in subtle frequency fluctuations. As a result, the signals are asynchronous to each other. please note.
Workaround for metastability
The two most common ways to reduce the effects of metastability are:
・ 同期用フリップフロップを使用する
・ FIFO ロジックを使用する
これらを簡単に説明します。
同期用フリップフロップの使用
A common metastability countermeasure is to insert multiple synchronizing flip-flops in the receiving side clock domain at the later stages, as shown in Figure 3, in order to synchronize the asynchronous input signal with the system clock. However, although the number of inserted flip-flops greatly improves the reliability of the system, the latency of the system increases by the number of inserted flip-flops, which may cause the performance of the entire system to deteriorate. there is.
If the difference between the repetition frequency of the asynchronous input signal and the frequency of the system clock is negligible, one stage is sufficient, but if the two frequencies are adjacent to each other, several stages may be used. You can find out how many stages to insert by checking the MTBF (mean time between failures) with the TimeQuest timing analyzer function of Quartus® Prime. In addition, it is recommended to shorten the FF interval on the receiving side so as to shorten the metastable period.
In Figure 3, even if the synchronizing flip-flop (the preceding flip-flop) produces a metastable output, then the metastable signal may stabilize before the second flip-flop is triggered. This method does not guarantee that the second flip-flop will not trigger an unstable output, but it does improve the probability that the data will be in a valid state before reaching the rest of the circuit. In this way, the number of stages of flip-flops to be inserted is determined based on the reliability required for the system.
In any case, do not feed more than one flip-flop with a single asynchronous input. Feeding a single asynchronous input to multiple flip-flops increases the probability of system error due to metastable conditions. This is because when an asynchronous input signal is input to multiple flip-flops, it is possible that each connected flip-flop will be in a different state, making it impossible to define a unique state in the system. In such a case, insert a synchronizing flip-flop and supply the output after defining a unique state for the system to the subsequent flip-flop or logic.
FIFO ロジックの使用
First-In First-Out (FIFO) logic is used to simultaneously synchronize multiple bits of input such as a data bus. FIFO logic uses synchronizers to pass control signals between two clocks, and data is read/written to dual-port memory. Figure 4 shows the schematic diagram.
At the end
システムに非同期の信号が入力されると、メタステーブルと呼ばれるシステム上予測不可能な状態に陥ります。最悪の場合、システムがハングアップし電源を切断しないと復帰しない事態を引き起こす場合があります。システム全体で同期化されていない機器間での信号の授受の場合には、メタステーブル状態を引き起こす可能性があります。したがって、システム全体の信号系統を精査し、同期化システムを構築し、不安定要素を取り除くことをお勧めします。
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