explanation

As the speed of the external memory interface (EMIF) increases, the shrinking of the data valid window (valid window of data) and the deterioration of signal quality have become issues.

In particular, board designers must pay attention to signal quality at the receiving end.

This document was created with the aim of reducing the risk of design failure and reversion by guiding the procedure for checking the board layout design and FPGA settings while paying attention to signal quality.

Target device: Intel® Arria® 10 FPGA
Target memory topologies: DDR4, DDR3

<Contents>

■Introduction
・Layout flow
・Pin & resource confirmation
・Check the layout
・Extraction of substrate parameters
・Board SIM with IBIS
・Confirm board SIM result
・Reflect board SIM results in IP
・Consider compilation results
・Final decision
・Actual waveform confirmation (option)

■Appendix
・How to create Example Design
・How to check parameters
・Confirmation items of the circuit diagram
・Confirmation items for board SIM results

Document