1. Check the support status of DDR4 SDRAM interface

For the support status of DDR4 SDRAM interface, refer to "Implementing an External Memory Controller in an Intel® FPGA!" ], you can check with the external memory interface spec estimator.

We will put conditions into the external memory interface spec estimator. Click the "Confirm search conditions and items" button such as the Arria® 10 (model number: 10AX115S2F45I1SG) mounted on the Intel® Arria® 10 GX FPGA development kit used in this verification, memory, board specifications, etc. Let's put in a condition.

• Family: Arria® 10 GX and GT
• Temperature Range & Speed Grade: Industrial Temperature Range (I), -1
• Interface type: hard
• Memory standard: DDR4
• Memory Topology & Rank: Components, UDIMM

The search results are as follows. The I1 in the last part of the part number indicates the temperature range & speed grade.

From this result, you can see that even for components (memory devices), chip selects are 1/2/4 and the upper limit of the maximum frequency of the memory interface is different. UDIMM (Unbuffered DIMM) also has different maximum frequency limits for single rank and dual rank.

Now let's use the Intel® Quartus® Prime software to actually generate the controller!

2. Configuring DDR4 SDRAM Controller IP

You can easily search for Arria 10 External Memory Interfaces by launching Quartus® Prime and entering Arria 10 External... in the IP Catalog search bar. (The Standard Edition of Quartus® Prime can work without a project open, but the Pro Edition cannot work without a project open.)

Click Add to launch the IP Parameter Editor and open a screen to enter the name and target device. Here: The target device is the device implemented in the Arria® 10 GX FPGA development kit.

• Entity name: ddr4
• Save in folder: C:\Work\a10_ddr4_1710
• Family: Arria 10
• Device: 10AX115S2F45I1SG

Click OK to display the IP Parameter Editor. Let's make the necessary settings!

Parameters in the center is an area where various necessary settings are made, and Details on the upper right has links to documents and descriptions of each setting item.

In Presets, representative memories are registered in advance. To test with the Arria® 10 GX FPGA development kit, we will use the DDR4 daughter card (Arria 10 GX FPGA Development Kit with DDR4 HILO) that comes with the development kit, so select it and click Apply. To do. Then most memory parameter settings will be reflected automatically.

Then, on each tab in Parameters, we will make the necessary settings to check the operation this time. Leave the other settings as default. For a detailed explanation of each setting, please check the Details mentioned earlier.

General tab

Make sure Protocol is DDR4. This should have been automatically reflected in the Presets earlier.

Next, make sure the Speed Grade (FPGA speed grade) is I1. I selected the target device at the same time as the name of the controller earlier, but that information should have been automatically reflected.

Leave the other settings as default. By the way, the memory interface frequency is 1066.667MHz.

Diagnostics tab

Simulation Options - Calibration mode

This setting is valid only for simulation and does not affect the operation of the actual machine.

The DDR4 SDRAM interface cannot be read/written immediately after power-on, and initialization and calibration are performed first. Detailed explanation is omitted here, but access such as read/write is not possible without following these steps.

This calibration can be skipped in simulation. Of course, you can check the full calibration movement by simulation, but depending on the configuration, it will take a considerable amount of time.

• Skip calibration: skip calibration
• Full calibration: Execute without skipping calibration

Example Designs tab

Example Design Files

• Simulation
  Check this box when simulating with Example Design.
• Synthesis
  If you want to check the actual machine with Example Design, please check it.

Generated HDL Format - Simulation HDL format

Select the HDL to simulate.

Target Development Kit - Select board

Select the target board. However, in the Presets mentioned above, we have set to use the Arria 10 GX FPGA Development Kit with DDR4 HILO that comes with the Arria® 10 GX FPGA development kit, so it should be selected.

Save this setting when you are done. Select File menu ⇒ Save As in IP Parameter Editor and save it as ddr4.qsys here.

Next, generate the Example Design. Click Generate Example Design, specify where to generate the Example Design, then click Generate. This time I specified C:\Work\a10_ddr4_1710\example_design as the generation location.

It will take a few minutes to generate the Example Design. If it can be generated successfully, the following window will be displayed, so click Close.

This time, we will check the operation with Example Design, so we will not generate a controller. If you plan to implement a controller in your FPGA design, please generate the controller.

When Example Design is generated, a qii folder, a sim folder, etc. will be generated.

3. Running a functional simulation

Try running a functional simulation. The files required to run the simulation (simulation project, testbench, traffic generator, memory model, etc.) are automatically generated when the controller is generated, so you can easily simulate.

In simple simulation terms, addresses, commands, and data are sent from a clocked traffic generator to the memory controller and written to memory through the PHY. The data read from memory is then compared with the data written. Success = High if they match, Fail = High if they don't match.

This time, we will simulate using ModelSim® - Intel® FPGA Edition.

After launching ModelSim® - Intel® FPGA Edition, select File menu ⇒ Change Directory to specify the working directory. This time, specify C:\Work\a10_ddr4_1710\example_design\sim\ed_sim\mentor. ModelSim® is a Mentor Graphics® simulator, so specify the mentor folder.

Then, in the ModelSim® - Intel® FPGA Edition Transcript window, run the commands in the following order:

1. do msim_setup.tcl (execute script for simulation)
2. ld_debug (compile library/compile design files/load design)
3. add wave "ed_sim/*" (capture signal in wave window)
4. run -all (run the simulation)

Although it depends on the PC specs, it took about 30 minutes to complete the simulation with ModelSim® - Intel® FPGA Edition with this configuration. (By the way, Questa® Prime/Core finished in about 4 minutes.)

When the simulation is finished, it will stop automatically. Click No when the simulation is complete and you want to check the waveform. (Please note that clicking Yes will close ModelSim® - Intel® FPGA Edition.)

Looking at the simulation waveform, you can confirm that ***_local_cal_successis​ ​High when intermediate calibration is completed. Calibration waveforms are omitted in Skip Calibration simulations.

Also, the simulation is complete when ***_traffic_gen_pass goes High. The Example Design repeats the operation of writing/reading and comparing, but the simulation ends after the first week. However, it can be used for long-run tests because it continues for a long time in the actual machine confirmation.

4. Compiling the Example Design

Next, prepare to compile the Example Design. Below is a block diagram of the Example Design.

Various settings, constraints, and pin assignments are required to compile, but the Example Design generated for the Arria® 10 GX FPGA Development Kit already has various settings, constraints, and pin assignments. Just in case, let's take a look at Pin Planner. Select Assignments menu ⇒ Pin Planner in Quartus® Prime.

Let's actually compile. Select Quartus® Prime Processing menu ⇒ Start Compilation.

Did the compilation finish normally?

<Supplement>
The timing analysis result (TimeQuest Timing Analyzer in the compilation report) is in red. This is due to the lack of timing constraints for all pins. However, the unconstrained pins are reset, JTAG related, and LED output pins, so we will proceed as is for now.

If there is a timing violation in Setup or Hold, try changing the compile settings. Set to Performance in the Quartus® Prime Assignments menu ⇒ Settings ⇒ Compiler Settings ⇒ Optimization mode. This setting aims to compile performance-oriented, so it tends to improve timing, but there are cases where it consumes a lot of resources.

5. Operation check using development kit

After the compilation is complete, write the SOF file generated by the compilation to the Arria® 10 device. Connect the development kit and PC with a USB cable (development kit side: USB Micro-B) and turn on the power.

<Supplement>
Intel FPGAs have a JTAG port. Write data through this JTAG port through the Intel® FPGA Download Cable.

Normally, you would use an Intel® FPGA download cable (such as USB-Blaster™ or USB-Blaster™ II), but the Arria® 10 GX FPGA development kit has Blaster functionality implemented on board, so you have to download it separately.・Data can be written using only a USB cable, without the need to prepare a cable.

Mount the included DDR4 daughter card in the center of the development kit.

Also check the JTAG chain setting (DIP switch/SW4 on the back).

• 1: OFF (left side)
• 2: ON (right side)
• 3: ON (Right side)
• 4: ON (Right side)

Then select Tools menu ⇒ Programmer in Quartus® Prime to launch the Quartus® Prime Programmer.

If the Programmer starts and the SOF file for writing is automatically registered, confirm that Hardware Setup and Mode are selected, then click Start to execute writing.

If the SOF file is not registered in the Programmer, set the download cable, mode, and write file as follows, then click Start to execute the write.

• Hardware Setup: USB-Blaster™ II (Cannot be selected unless the USB-Blaster™ II driver is installed) ⇒ How to install the USB-Blaster™ II driver
• Mode: JTAG
• Add File: SOF file generated during compilation (file name: ed_synth.sof)

After writing the SOF file, the Example Design actually works. In normal operation, the green LED should be on.

The LEDs are assigned as shown in the table below. These pin assignments are also automatically assigned in the Example Design for the development kit.

You can also monitor internal FPGA signals using the Signal Tap logic analyzer feature. I would like to introduce this on another occasion.