Introduction video

FPGA Functional Verification Trends and Challenges

Introducing ModeiSim / QuestaSim

Introduction to Logic Simulator

Questa Sim and ModelSim are widely used logic simulators worldwide. It supports hardware description languages (HDL) such as Verilog, SystemVerilog, and VHDL, and allows mixed simulation of these languages.

Compare Products (Editions)

Depending on the edition, the simulation speed and the debug functions included differ. As recent FPGA designs have become larger in scale, debug functions other than functional simulation are very popular.

Introduction to debug functions

Questa Sim and ModelSim features are introduced here.
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Assertion-based verification

By placing assertions inside the circuit, it automatically monitors for unpredictable behavior.

code coverage

Detects HDL descriptions that are not toggling in simulation. Detect areas and input conditions not covered by the testbench.

Waveform comparison

Compare the logic-validated baseline data with the simulation results under investigation.

Extended data flow

A circuit diagram around the relevant signal is automatically generated from the RTL, and it is possible to identify the cause by time traceback and backtrace the indeterminate value X.

Related information

▶ How to download the Siemens EDA tool
▶ How to install Questa / ModelSim
▶ How to license Siemens EDA tools

Seminar/Workshop

▶ [Online Seminar] Basics of logic simulation and how to use debug functions <Free>

This seminar will introduce the basic simulation flow and basic debugging functions using the Questa Advanced Simulator.

▶ Related events and seminars

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