What is code coverage?

A function that counts each execution in the HDL code while the simulation is running.

・ "To what extent" was the simulation performed with the prepared test pattern for the HDL design to be verified? is evaluated quantitatively.
・ If there are unverified parts, review the RTL or add test patterns.

Benefits of using code coverage

● Improve test quality

If code coverage doesn't execute a "needed function", then there is a hole in the test. You can add testbenches to improve test quality.

● Reduced circuit area (cost reduction)

If the part that was not executed by code coverage is an "unnecessary function", the corresponding HDL description can be deleted to reduce the circuit area.

● Improved credibility from FPGA development requesters and project managers

Clients and project managers who outsource FPGA development to design houses are blind to the test quality and circuit overhead of the designs they outsource. By reporting the high coverage rate of code coverage to the development requester and project manager, you can appeal that you are conducting highly reliable development.

Types of code coverage

Questa Sim / ModelSim supports different types of code coverage.

(1) Statement coverage: for each statement

- Even if multiple statements are written in one line, the coverage is counted for each statement.
・ Report execution count for each statement

Example: if sig1 then hit <= '1' ; out <= '1' ; else hit <=………;

(2) Branch coverage: conditional branching

- Counts whether or not all branch destinations have been executed in conditional branches such as if statements and case statements.
・ Reports the number of times conditional branches have been passed, the number of true/false times in if statements, the number of times each option verified in case statements, and the number of executions at branch destinations.

Example: if ( a or b ) then

(3) Condition coverage: combination of conditions

- The extended branch coverage function measures the number of executions of combinations of branch condition inputs and outputs.
• Analyze logical combinations of variables and conditions within conditions.
・ Reports the number of times for combinations of variables and conditions that lead to truth.

Example: if (a or b) then 4 combinations in this example

(4) Expression coverage: combination of expressions with assigned values

- Similar to condition coverage, but measures the number of executions of the expression on the right side of the assignment statement.
• Analyze logical combinations of variables in expressions that have values to be assigned.
• Report counts for combinations of variables in expressions.

Example: a <= b or c ;

(5) FSM coverage: state/transition

・ Measure the number of transitions of the logic state machine. Reports whether each state was executed, transition executed, and the number of executions per state.

(6) Toggle coverage: Toggle state

・ Measure the number of times the signal changes between 0 and 1 (is it activated?) and the number of times it toggles (changes).

Coverage range control

You can control the coverage target by the following methods.

● Loading and saving Exclusions files
● Specify from Missed Coverage (Exclude setting)
● Insert a dedicated pragma in HDL (automatically set the code between pragmas to be excluded)

▶ assertion validation
▶ code coverage
▶ Waveform comparison
▶ Enhanced dataflow

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