Flow of FPGA development

Roughly speaking, FPGA development consists of 8 processes (2 to 9 in the figure below). The 3rd and 5th to 9th steps are performed in Quartus® Prime, and the 4th step is performed in an EDA simulator such as Questa* - Intel® FPGA Edition.
Please refer to the Intel® FPGA development flow page for the operation manuals of the tools for each process.

1. Preparation

FPGA 開発ソフトウェア Quartus® Prime を使用するためのパソコン環境の整備や、開発ソフトウェアのセットアップなど、準備をします。
詳細は以下のページを参考にしてください。

開発に必要なパソコン環境について

• ほんとのほんとの導入編 その1. FPGA 開発をはじめるための環境づくり

開発ソフトウェアのセットアップについて

• Intel® FPGA Development Flow/1.Preparation

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2. Examination of functional specifications

Based on the system specifications, consider the functions to be implemented in the FPGA (how to process them), and summarize them in specifications such as block diagrams, external interfaces, and inter-block interfaces.

Also, select a family of FPGAs that meets the specifications.

If you plan to use the internal functions inherent in the FPGA, such as PLL (Phase Locked Loop), multiplier block, RAM block, etc., use the FPGA development software Quartus® Prime in advance. Or, use a simulator such as Questa* - Intel® FPGA Edition to create a simple sample design and perform logic verification (RTL simulation) to check operation.

　　
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3. Logic circuit design

HDL (Hardware Description Language) such as VHDL, Verilog-HDL, SystemVerilog, etc. is used to describe the behavior of logic circuits. Although it is possible to design with a dedicated schematic (schematic) editor, designing using language has become mainstream in recent years. These descriptions are mainly called “designs”.
HDL can be written using a general-purpose text editor, but the built-in text editor of Quartus® Prime is a general-purpose text editor that allows you to insert templates and sample designs, and conveniently display characters in different colors according to grammar. It is recommended because it has some ingenuity that is not found in the standard.
Also, like C programs, HDL varies in circuit size and speed depending on how it is written. Quartus® Prime automatically processes user-designed designs optimally according to the architecture of the target device.

To use the functional blocks (multipliers, memories, PLLs, transceivers, etc.) built into the FPGA, use a tool called the Quartus® Prime IP Catalog. Select a pre-built dedicated block from the IP Catalog and customize it by selecting and modifying port configurations and parameters. The files are then generated, connected and incorporated into the user's design. (IP stands for Intel® FPGA Intellectual Property)

インテル® FPGA Intellectual Property に関する情報は、以下をご覧ください。

• Introduction to Intel® IP Cores

• Intel® FPGA Intellectual Property

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4. Logical simulation

A simulator such as Questa* - Intel® FPGA Edition is used to check (verify) the logic operation on a personal computer to see if the operation of the designed logic circuit (design) meets the user's requirements.

The method of checking the simulation execution results is mainly to use graphically displayed waveforms. If there are operating points that differ from the specifications, it means that the description of the designed logic circuit is incorrect, so correct the description. , and check the behavior again in simulation. Repeat this process to complete the description of the logic circuit.
At this time, input signal data (also called test pattern or test bench) to the verification target circuit is required in addition to the design of the logic circuit realized by FPGA. The testbench allows the user to write test pattern information according to specifications in HDL language and load it into the simulator.
Since the testbench is written by the user, if this input pattern is different from the specification, the verification itself will be a waste of work.

If you are new to HDL design, please refer to sample sources such as reference books when writing.

テストベンチの記述に関しては、以下の記事も是非ご覧ください。

• Let's start! Test bench

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5. Constraint setting

In FPGA development, the user does the pin layout of the device themselves.

Depending on the placement environment of the FPGA and peripheral devices on the board, determine the location of the pins on the FPGA side so that the wiring is short.

Also, FPGA pins have various built-in functions, such as the ability to change the output pin drive current, internal pull-up resistors, and the ability to enable internal termination resistors. Applying the pin function to the device is accomplished by setting options and compiling in Quartus® Prime.
In addition, the operating speed of the FPGA is also set by the user as a timing constraint. Unlike ASSPs, which have fixed operating frequencies, FPGAs rely on the configuration of user-created logic circuits. Of course, there is a limit to the speed of FPGAs, so at the stage of considering adoption, it is necessary to select a family that has specifications such as the clock frequency to be introduced and the data transfer speed with peripheral devices that can be achieved, but the desired timing By setting conditions, the Quartus® Prime Compiler will realize the optimal gate configuration and placement.
These constraints need to be set and input in Quartus® Prime before compilation (logic synthesis and place-and-route). Graphical tools such as Pin Planner: left) and Timing Analyzer (timing analyzer: right) are used. Timing constraints are in the SDC format, which is standard in ASIC design. A wizard for creating the SDC code is also provided as an auxiliary function, so users who do not know the SDC format can easily describe timing constraints.

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6. Compile

After creating the design and setting various constraints, execute “Compile”.

Compilation is a general term for work that mainly performs "logical synthesis" and "placement and routing". Quartus® Prime initiates these tasks by simply clicking an icon on the screen, and then automatically performs them.
“Logic synthesis” is the work of converting a design created by the user in an HDL description language or a schematic into concrete gate circuits such as ANDs and flip-flops, which conforms to the structure of the FPGA used by Quartus® Prime. Automatically converts with the optimal gate configuration.
After that, according to the structure of the FPGA to be used, internal logic placement and pin positions are determined as specified by the user, and routing is automatically performed between logic and between logic and pins. This is called “place and route”.
When the compilation is finished, the results of various compilation processes are generated as a report, and the contents can of course be checked using the GUI.

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7. Timing Verification

The compilation report also contains timing analysis results.

The user must confirm whether the circuit implemented in the device operates at the required speed (whether the required values set by the timing constraints are met). Timing analysis results in the compilation report are only summary information, so to see detailed results, use the Timing Analyzer in Quartus® Prime and verify statically.
If the results do not satisfy the required values, use the Quartus® Prime options to change the placement and routing algorithm, apply the device functions, and recompile to change the internal layout. We will try to improve by doing so.

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8. プログラミングする

After the timing analysis shows that the circuit works correctly as requested by the user, the circuit data generated by Quartus® Prime is transferred from the personal computer to the FPGA in order to actually operate the FPGA on the development board. This is called “programming” (also known as downloading).

Users program using the Intel® FPGA Download Cable USB-Blaster™ II and a utility called Programmer that comes with Quartus® Prime.
Since many FPGAs use SRAM for their program elements, you must provide non-volatile memory for boot memory on your board. Intel® refers to the device for non-volatile memory as “configuration ROM”, and programs to this memory. The FPGA works only after data is transferred from this configuration ROM on the board. This is called “configuration”.
The only exception is the MAX® 10 FPGA family. MAX® 10 is a new type of FPGA with boot memory built into the device. Therefore, no external boot memory is required for MAX® 10.

Return to FPGA Development Flow Diagram

9. Actual equipment verification

After the board is powered on again and the data is successfully transferred from the configuration ROM to the FPGA, it enters the phase of checking the operation of the FPGA.
If there is a problem in operation, the signal is generally verified with a logic analyzer or oscilloscope, but for simple signal verification, Quartus® Prime has an on-chip debug function called Signal Tap. This is a debugging method (mechanism) that configures logicana inside an Intel® FPGA, and does not require any special equipment. With the USB-Blaster™ II on the cable, you are ready to debug. SignalTap is license-free and available in the free Quartus® Prime Lite Edition.

Signal Tap についてざっくり知りたい人、やってみたい人は、以下の記事をご覧ください。

• FPGA オンチップ・デバッグ " Signal Tap " をやってみよう

Signal Tap の詳細は、下記のメーカー資料および インテル® のホームページで公開されているオンライン・トレーニング（無料）をご覧ください。

• Design Debugging with the Signal Tap Logic Analyzer （Quartus Prime Standard Edition）

• Design Debugging with the Signal Tap Logic Analyzer （Quartus Prime Pro Edition）

なお、オンライン・トレーニングの受講方法は、下記コンテンツをご覧ください。

• インテル® FPGA テクニカル・トレーニングを無料で受講しよう

Return to FPGA Development Flow Diagram

10. Mass production

実機検証が完了すれば すぐに量産へ移ることができます。

The above is the general flow of FPGA development.

　
Let's give it a try! However, if you have never developed an FPGA before, it's reckless to start by thinking about the specifications. Let's start by imitating it.
Evaluation boards released by Intel® and Mpression (Macnica 's original brand) come with reference designs (sample designs) and user guides (manuals). You can download sample design data from the evaluation board page on the website before or after purchase, or even if you don't purchase the board.

There are other ways to get sample designs other than the evaluation board page. For details, please see the content below.

• Get Free Intel FPGA Example Designs

評価用基板が手元にまだなくても、作業3～作業7までの工程なら すぐに作業に取り掛かれます。まずはツール操作に慣れましょう。

ここで、（今回上記でご紹介した資料の他に）ツールに慣れるための “無料で受講できるトレーニング・コンテンツ” をご紹介します。

Quartus® Prime を使いこなせるかが FPGA 開発の近道と言っても過言じゃありません。操作マニュアルやトレーニング各種をフルに活用して、徐々に慣れていきましょう。何かわからないことがあれば、半導体製品専用 お問い合わせフォーム へお問い合わせください。

「ほんとのほんとの導入編」、このシリーズは次回で終了です。最終回の “その5” では、FPGA や CPLD を勉強するために便利な WEB サイトをご紹介します。

• ほんとのほんとの導入編 その5. 役立つコンテンツの紹介 へつづく

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