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The Intel® HLS Compiler is available in all editions (Pro/Standard/Lite) of the Intel® Quartus® Prime software starting with v17.1. Here is the most suitable information for users who will use the HLS compiler from now on.
What is an HLS compiler?
An HLS compiler is a High Level Synthesis (HLS) tool optimized for Intel® FPGAs, a so-called high-level synthesis tool. By using this tool, it is possible to create circuits (designs) for implementation on Intel® FPGAs from software programming languages such as C and C++.
Until now, software designers have been able to create designs that required knowledge of hardware. It is now possible to offload the circuit for the FPGA and optimize the system.
HLS compiler documentation
Visit this page to view the materials Intel has prepared.
HLS compiler introduction page (Intel)
(Click here for English version)
* For documents, please click the "Related Documents" (English page is "Document") tab.
The following materials are available.
- Product Summary
- Image Processing White Paper
- Getting started guide
- User guide
- Reference manual
- Best practice guide
- Quick reference guide
- White Paper "QRD Decomposition Optimization"
I've introduced several materials, but I'm not sure which order to refer to, right? In learning how to use the HLS compiler, I will introduce the reference order of the material so that you can understand the overall flow.
1. Product overview
A product overview of the HLS compiler. You can get a rough overview of the tool.
First, you need to know how to build the environment required to use the HLS compiler. In addition, it is also possible to grasp the contents of the Example Design in advance, which will be a reference when using the HLS compiler in the future.
Please see this article for how to build the environment for the HLS compiler.
HLS Compiler Environment Construction (Windows® Edition)
2. User Guide
After setting up the tool, learn the actual flow. The user guide will help you create your component using the HLS Compiler and walk you through the synthesis, verification and simulation steps.
Step-by-step instructions for synthesizing, verifying, and simulating IP designed for Intel® FPGA products. Information including basic commands for verification and simulation, such as creating a testbench for simulation during synthesis, is provided. Also included are instructions for using the generated IP in Quartus® Prime, limitations of the HLS Compiler, and a brief description of the report.
3. Best Practice Guide
Learn how to optimize performance with the HLS compiler. Specifically, loop optimization, optimal memory architecture configuration, component data type and conversion optimization for performance and logic area reduction.
Even if you actually create a component, if the performance is not as expected, perform the optimization described in the documentation. In this document, you can learn an example of where the bottleneck is using the tool and how to optimize it.
At a minimum, it is possible to learn all the functions of the HLS compiler by referring to the materials in the above order. You may also find useful information in other resources. Although it is not described in the above flow, please refer to it as necessary.
Additional resources are listed below.
Other materials
Image Processing White Paper
You can see the design flow of the HLS compiler using image processing as an example. It explains the algorithm, C++ implementation, and the flow from actual implementation to hardware using the HLS compiler, verification, and optimization.
It is the best material for understanding the flow from specification study to implementation and optimization, as it explains with specific examples what kind of flow should be implemented when using the HLS compiler.
Getting started guide
Information necessary for environment construction such as tools and license settings necessary for using the HLS compiler, introduction of Example Design, etc. is posted. It is a very useful resource for future users of the tool.
It also contains information on troubleshooting with licenses, so it will be helpful if you are having trouble setting licenses.
Reference manual
Refer to it when you have trouble specifying command options or component attributes.
Contains information necessary for actual design, such as HLS compiler command options, components, and interface attribute descriptions. Component attributes and interfaces are determined, and refer to them when editing source code or executing commands in the HLS compiler.
In addition, the appendix provides a list of command line arguments and component attributes as a click reference. It can also be used to search for arguments, commands, etc.
White Paper "QRD Decomposition Optimization"
You can understand the optimization method using eigenvalue decomposition as an example.
It provides an example of improving the performance of the code for QR decomposition using the optimization techniques presented in the best practices guide. In using the HLS compiler, you can understand the specific optimization method using an actual example.
Experience the HLS Compiler
このページで紹介した順番で資料を参照すれば、すぐに HLS コンパイラの評価を行うことができます。
HLS コンパイラを用いて、工数の削減やソフトウェア設計者がハードウェア設計を行う第一歩となれば嬉しいです。
環境構築の方法や簡易チュートリアルといった記事や資料を用意しています。ぜひ、HLS コンパイラを使用してみてください。
Click here for recommended articles/materials
HLS Compiler Environment Construction (Windows® Edition)
HLS simple tutorial
Articles and resources related to High Level Synthesis
Intel® FPGA Development Flow/FPGA Top Page