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Hello. My name is Taro Washimiya and I provide technical support for Intel® FPGA products at Macnica.
In "Intel® FPGA PLL", we provided an overview of FPGA PLL, but here we will explain the steps to use ALTPLL.
To see which FPGA families can use the ALTPLL, see PLLs in Intel® FPGAs.
content
tools to use
- Intel® Quartus® Prime Design Software
- ModelSim® - Intel® FPGA Edition
See the Quartus® Prime Edition Comparison for the relationship between target FPGAs and development tool editions.
If you don't have the development software installed, you can get it from the Intel® FPGA website.
For details, please see the content below.
How to Download Intel® Quartus® Prime Software and ModelSim® - Intel® FPGA Edition
How to Install Intel® Quartus® Prime Software and ModelSim® - Intel® FPGA Edition
1. Generate ALTPLL
Here we take MAX® 10 project as an example.
Open a project whose target device is MAX® 10 or create a new project.
(For information on how to create a Quartus® Prime project, refer to Quartus® Getting Started Guide - How to Create a Project.)
Type pll into the IP Catalog search bar within Quartus® Prime.
Then you can easily locate the ALTPLL.
With ALTPLL highlighted, click Add.
Specify the folder path to generate the ALTPLL, the name you want to give to the ALTPLL, the language to generate (VHDL or Verilog), and click OK.
It is recommended to generate in the working folder of the project or its lower folder.
The ALTPLL parameter setting window will open.
If you want to see detailed documentation and explanations of each setting item here, click Documentation.
This section provides an overview of the main setting items in each tab.
For details on each item, see the user guide from the link to the document introduced earlier.
Parameter Settings tab
General/Modes
Make general settings such as the reference clock (input clock) frequency, PLL type, and PLL operation mode.
Here, as an example, we will make the settings shown in the table below.
|
What is the frequency of the inclk0 input? (input clock frequency) |
50 (MHz) |
|
How will the PLL outputs be generated? (PLL mode) |
In normal mode |
Inputs/Lock
Set optional signals of ALTPLL such as asynchronous reset signal and PLL lock signal.
PLL Reconfiguration Tab
Make settings related to PLL reconfiguration.
This example does not use the reconfiguration feature.
Output Clock tab
Set the multiplication ratio, division ratio, phase shift, etc. of the clock generated by the PLL.
Also, the number of clocks that can be generated by the PLL is device dependent.
This time, set as follows.
|
clk c0 |
clk c1 |
|
| Clock multiplication factor |
2 |
2 |
| Clock division factor |
1 |
1 |
| Clock phase shift |
0 (deg) |
90 (deg) |
EDA tab
Make a note of the library name that is required during simulation.
Summary tab
Specify the file to be automatically generated when ALTPLL is generated.
After finishing various settings, click Finish to generate the IP.
After confirming "Generation Successful" and clicking Exit, the following window will appear.
Click Yes to add the generated IP design to the currently open project. (If you click No, please add it manually.)
ALTPLL generation is now complete.
Let's proceed with logic design by connecting with the user circuit you are designing.
If you want to change the ALTPLL parameter settings, please see this FAQ.
[FAQ] How to start IP editing screen
After editing the necessary parts, generate ALTPLL again.
2. Connection with user circuit
Once the ALTPLL is generated, connect it with user logic.
If you are not familiar with Verilog-HDL or VHDL, please refer here. See Calling Subordinate Modules (Blocks) within this page.
Let's start! Verilog-HDL <with exercises>
Let's start! VHDL <with exercises>
If you are designing with a schematic (circuit diagram), a symbol for the schematic editor is also generated when the IP is generated, so please call and connect the IP symbol created by the user on the schematic editor.
However, the schematic cannot be RTL simulated in 3rd party tool simulators. Again, it is recommended to design in HDL.
<Tricks>
If you are not familiar with writing HDL, try using the schematic-to-HLD conversion feature in Quartus® Prime's schematic editor.
Please refer to here for how to convert.
Getting Started with Quartus® - Using the Schematic Editor
After creating the upper layer design file,
Select Processing > Start > Start Analysis & Synthesis from the Quartus® Prime menu to perform logic synthesis.
Did it complete successfully?
When converting from a schematic, if both the schematic file (BDF file) and the converted HDL file (V file for Verilog-HDL, VHD file for VHDL) are registered in the project, logic synthesis cannot be performed properly. . (Remove unused design files from Project menu > Add/Remove Files in Project.)
3. Check by simulation
Now let's check the behavior in RTL simulation.
This time we will use ModelSim® - Intel® FPGA Edition.
A testbench is required for verification in simulation, but the testbench is created by the user.
See here for instructions on how to create a testbench.
Let's start! Test bench
Once you have your testbench, you are ready to simulate!
You can also manually simulate in ModelSim®, but here is a convenient method. please refer.
Simulation using NativeLink functionality
Let NativeLink solve your FPGA function simulation
Let's generate and run a simulation script file for ModelSim®
Simulating with msel_setup.tcl
How to edit and use msim_setup.tcl
So far, Taro Washinomiya introduced the procedure from creating an ALTPLL to simulation.
Click here for recommended articles/materials
PLL division/multiplication
Application of PLL (Let's reduce EMI with spread spectrum!)
The intimate relationship between PLL loop bandwidth and spread spectrum
PLLs in Intel® FPGAs
List of IP-related articles and materials
Intel FPGA Development Flow / Top Page