Purpose of this course

Overview

The Intel® High Level Syntheis (HLS) Compiler is a high-level synthesis tool that takes C++ as input and generates RTL (register transfer level) code optimized for Intel® FPGAs.

In this seminar, you will learn hands-on how to use the Intel HLS Compiler to synthesize and verify IP components for Intel FPGAs.

We will first discuss the benefits of HLS and the capabilities of the Intel HLS Compiler. It then describes the design flow using the HLS compiler with a series of compiler options, generated reports, and how to use the final generated files to integrate the IP into your Intel® Quartus® project.

Target audience

・FPGA designers who want to learn the overview and flow of the Intel HLS Compiler

goal of attending

・Understanding the concept of high-level synthesis in Intel® FPGAs
・Understanding the design flow using the HLS compiler
- Algorithm verification by emulation
- Functional verification by co-simulation
- How to check the report
- How to include HLS components in your Quartus® Prime project
・Understanding of interfaces and control methods that can be used in components generated by HLS

agenda

1. Introduction to HLS 1 ～Introduction～
2. Introduction to HLS 2 ～x86 emulation～
3. Introduction to HLS 3 ~ Co-simulation ~
4. Intel Quartus Software Integration
5. How to check the HLS report
6. HLS interface

1. HLS Introduction 1 ~Introduction~

This chapter introduces the overview and flow of high-level synthesis using the Intel HLS Compiler.

(Duration: 9 minutes 29 seconds)

2. HLS introduction 2 ~x86 emulation~

This chapter describes the emulation steps of the HLS compiler.
In emulation, an x86 executable file is generated and functional verification of the created function is performed using the software verification environment.

(Duration: 3 minutes 49 seconds)

3. Introduction to HLS 3 ~Cosimulation~

This chapter describes the co-simulation steps of the HLS compiler.

Co-simulation generates your function as an HDL IP component.

Validate the generated HDL by simulation.

(Duration: 14 minutes 12 seconds)

4. Intel Quartus Software Integration

This chapter describes how to add and use HDL IP generated by the HLS Compiler in your Quartus® Prime project.
- How to instantiate in HDL
- How to add and use it as an IP in Platform Designer

(Duration: 5 minutes 38 seconds)

5. How to check the HLS report

This chapter explains how to check logic and memory resource usage, loop structure, data flow, etc. from the HDL generation report.

(Duration: 12 minutes 03 seconds)

6. HLS Interface

When generating an HDL IP component with the HLS compiler, you need to consider what kind of interface you want the IP to have.
This chapter introduces the types of interfaces and how to control them using description styles, attributes, etc.
- default HLS interface
- Memory mapped master interface
- explicit streaming interface
- Slave interface

(Duration: 13 minutes 08 seconds)