Purpose of this course

Overview

In this seminar, you can learn the overview and operation flow of the Intel® Quartus® Prime  development tools necessary for Intel® FPGA development.

We also publish the exercise manual and exercise data as hands-on.

If you use the development board during the exercise, you can experience the exercise while operating it on the actual machine.

(Some exercises can be performed without a development board.)

Target audience
・People who want to know the overview of FPGA development flow
・People who are starting or considering Intel® FPGA development
- New to Intel® Quartus® Prime
・Those who have already developed an FPGA but want to review the basic operations of Intel® Quartus® Prime
・People who are considering taking Intel FPGA official training
- As a preparation

goal of attending

・Learn how to install Intel® Quartus® Prime
- How to download, how to install, how to get and set license files

・Know the overall flow of FPGA development

・Learn the basic operation of Intel® Quartus® Prime

・Hands-on experience with Intel® Quartus® Prime (hands-on users only)

agenda

1. Intel® FPGA Product Introduction
2. Download and Install Intel® Quartus® Prime
3. Obtaining and setting the license file
4. Intel® Quartus® Prime Overview
5. Basic Intel® Quartus® Prime Operations
6. Intel Official FPGA Training Introduction

Intel® FPGA Product Introduction

This chapter introduces the Intel® FPGA device family.

(Duration: 4 minutes 00 seconds)

 

[Content introduced in this chapter]

・ Product Selector Guide

・ Useful tools for selecting Intel® FPGA devices and IP

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Download and Install Intel® Quartus® Prime

This chapter introduces how to download and install Intel® Quartus® Prime.

(Duration: 6 minutes 22 seconds)

 

[Content introduced in this chapter]

・ How to download Intel® Quartus® Prime software and ModelSim® - Intel® FPGA Edition

・ How to install Intel® Quartus® Prime software and ModelSim® - Intel® FPGA Edition

・ Quartus® Prime Supported Device List

・ Operating System Support

・ Quartus® Prime Support Windows OS Correspondence Table

・ Intel® Quartus® Prime Pro Edition Software and Device Support Release Notes

・ Intel® Quartus® Prime Standard Edition Software and Device Support Release Notes

・ How to register in My Intel (Intel® FPGA Program)

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Obtaining and setting the license file

This chapter introduces how to obtain and configure a license file.

(Duration: 2 minutes 30 seconds)

 

 

[Content introduced in this chapter]

・ How to acquire a license when purchasing a new license

・ Fixed license setting method for Intel® Quartus® Prime and IP

・ How to set Intel® Quartus® Prime and IP floating license

・ Quartus® Prime license format

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Intel® Quartus® Prime Overview

This chapter provides an overview of what kind of development software (tool) Intel® Quartus® Prime is, and confirms the basic operation flow.

(Duration: 3 minutes 27 seconds)

 

[Content introduced in this chapter]

・ Intel® FPGA development flow/FPGA top page

・ Let's try FPGA on-chip debugging “Signal Tap”

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Basic Intel® Quartus® Prime Operations

This chapter introduces the following flow of Intel® Quartus® Prime operation flow.

Please scroll the screen to the chapter you want to see.

 

・Creating a project

・Design creation

・Logic simulation

・Constraint setting (pin layout etc.)

·compile

・Timing verification

·programming

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Create a project

This chapter introduces how to create a new project.

(Duration: 2 minutes 20 seconds)

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Create a design

This chapter describes the design entry methods supported by Intel® Quartus® Prime, Analysis & Elaboration, and the Message window.

(Duration: 5 minutes 52 seconds)

 

[Content introduced in this chapter]

・ Let's try it for the first time! VHDL <with exercises>

・ Let's try it for the first time! Verilog HDL <with exercises>

・FPGA のサンプル・デザインを無料で手に入れよう

 

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Logical simulation

This chapter describes functional simulation using Modelsim® - Intel® FPGA Edition.

(Required time: 6 minutes 06 seconds)

 

[Content introduced in this chapter]

・ Let's try it for the first time! Test bench

・ ModelSim® - Intel® FPGA Edition - How to do RTL simulation

・ Let's solve FPGA function simulation with NativeLink

・ How to use ModelSim® to functionally simulate a design containing IP generated by Intel® Quartus® Prime Pro Edition

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Constraint setting (pinout etc.)

In this chapter, we will introduce typical constraints that are performed before compilation.

(Duration: 8 minutes 47 seconds)

 

・Pin assignment and I/O standard setting

・Set unused user I/O pins

・Configuration settings

・Other option settings

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compile

This chapter introduces how to compile and the reports that are generated.

(Duration: 3 minutes 13 seconds)

 

・Compile execution

・Compile report

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timing verification

This chapter introduces timing verification.

(Duration: 3 minutes 09 seconds)

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programming

This chapter introduces programming.

(Duration: 4 minutes 51 seconds)

 

[Content introduced in this chapter]

・ Programming to EPCQ device via FPGA (JIC programming)

・ Install the USB-Blaster II driver

・ Install the USB-Blaster driver

・ Try changing the TCK frequency of the USB-Blaster II

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Actual machine verification

This chapter introduces you to the Signal Tap logic analyzer.

(Duration: 2 minutes 25 seconds)

 

[Content introduced in this chapter]

・ Let's try FPGA on-chip debugging “Signal Tap”

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Intel® Official FPGA Training Introduction

This chapter introduces Intel official FPGA training.

(Duration: 1 minute 23 seconds)

For technical training and seminars on ^Intel® FPGA products, please visit the Intel FPGA Seminars & Training top page.

Of these, the Intel official FPGA training related to this course is the following two courses.

・ [B-2] Quartus® Prime Perfect Course I

・ [B-3] Quartus ® Prime Perfect Course II : Timing Analysis

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practice content

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