Intel® Quartus® Prime Design Software - Semiconductor Business -Macnica

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Overview

intel ^® Quartus ^® Prime development software is Intel ^® Development tools for designing FPGAs, SoCs and CPLDs.
From design entry to logic verification, logic synthesis, placement and routing, timing verification, power consumption analysis, pin assignment, and device
It has the functions necessary for the development flow of

Three Editions of Intel® Quartus® Prime

The ^Intel® ^Quartus® Prime software is available in three editions: Lite, Standard, and Pro.
Each edition has differences in available devices and optional features.

License Comparison Table (18.1)

●: Support, ▲: Optional (separate cost required)

	Main function	light edition (free of charge)	Standard edition (paid)	Professional edition (paid) 1 1: Standard edition with Pro edition license is also available, but the software must be installed separately Is required.
*Device support 2** 2: Supported devices differ depending on the version. See “Note:”* below the table for details	Low cost FPGA/CPLD (Cyclone ^® 10 LP, MAX ^® 10, etc.)	●	●
	General FPGA/CPLD (Cyclone ^®, MAX ^®, Arria ^®, Stratix ^® series, etc.)		●
	Latest high-end FPGA (^Intel® Cyclone ^® 10 GX, Arria ^® 10, Stratix ^® 10, etc.) ^Intel ^Arria 10 Available in Both Standard and Pro Editions		●	● 3 3: ^Intel® ^Cyclone® 10 GX uses Pro Edition, Can be used without a Pro Edition license
design entry/ planning	Multi-processor support Fast compilation using multiple processors		●	●
	Free key IP including IP base suite DDR3 controller	▲	●	●
	Platform Designer (Standard) (Formerly: Qsys) Easily connect self-made designs and IP connections using a GUI	●	●
	Platform Designer (Professional) (Formerly Qsys Pro) Fast version of Platform Designer			●
	Design Partition Planner Optimize design partitions and improve fitting efficiency		●	●
	Chip Planner Graphically set and check floor plan and placement and routing information	●	●	●
	Interface Planner (formerly BluePrint) Optimize I/O designs with complex constraints without repeated recompilation, reducing I/O design time			●
	Logical simulation	ModelSim ^®- Intel FPGA Starter Edition Free Logic Simulator	●	●	●
ModelSim ^®- Intel FPGA Edition 33% faster logic simulator than Intel FPGA Starter Edition	Logical simulation	▲	▲	▲
logic synthesis	Convert logic synthesis HDL to netlist	●	●	●
Placement/wiring	Mapping fitter netlist to target FPGA/CPLD	●	●	●
	Fixed the placement and routing information of the logic lock region specific block to ensure the performance after recompilation		●	●
	Faster fitting time by splitting stages of incremental optimization fitting			●
	Reduce convergence time by initial placement considering initial placement timing			●
	Register retiming Move the register position before and after the worst path improve timing		●	●
	Hybrid placer New placement algorithm speeds up placement time		● 4 4: ^Intel® ^Arria® 10, ^Stratix® V, ^Arria® V Available for : and Cyclone ^® V	●
design flow	Partial Reconfiguration Reconfigure only the inactive portion of the circuit while the FPGA is running		● 5 5: Only available for Cyclone ^® V and Stratix ^® V	●
	Rapid recompilation Shorten compile time by targeting only changed parts when recompiling		● 6 6: Available for Stratix ^® V, Arria ^® V, and Cyclone ^® V	●
	Block-based design Convenient function for team design to design blocks separately			●
timing and power verification	Timing Analyzer (formerly TimeQuest) Static timing analysis using industry standard SDC	●	●	●
	Design Space Explorer II Automatically finds different optimal compilation settings and algorithms for each design	●	●	●
	Power consumption analyzer (Formerly: PowerPlay Power Analyzer) Analyze power consumption	●	●	●
In-system debugging	Signal tap (old: SignalTap II) Waveform display of FPGA internal signals running on the actual device without using external pins	●	●	●
	Transceiver Toolkit Fast Jitter-Noise, Eye-Diagram Analysis for High-Speed Serial Links		●	●
	^Intel® Advanced Link Analyzer (Formerly JNEye) Analyze Jitter/Noise I-Link on High-Speed Serial Links		●	●
OS support	Windows/Linux (64-bit)	●	●	●
Additional software	intel ^® FPGA SDK for OpenCL ^TMs Generate kernel functions for processors from OpenCL C language (for accelerator development using FPGA)	●	●	●
	^Intel® HLS Compiler C++ Generates HDL Optimized for ^Intel® FPGAs	●	●	●
	DSP Builder for Intel ^® FPGA Generate HDL for digital signal processing using MathWorks Simulink tools (Also see "DSP Builder for Intel FPGA", "MathWorks ^®, MATLAB/Simulink ^®"," MathWorks ^® Fixed-Point Designer" required)	● 4 4: Available for ^Intel® Arria ^® 10, Stratix ^® V, Arria ^® V and Cyclone ^® V	● 4 4: Available for Intel ^® Arria 10, Stratix ^® V, Arria ^® V and Cyclone ^® V	● 4 4: Available for ^Intel® Arria ^® 10, Stratix ^® V, Arria ^® V and Cyclone ^® V
	Nios ^® II Embedded Design Suite (EDS) Nios ^® II software development package (Nios ^® II hardware design requires a separate license)	▲	▲	▲
	Intel SoC FPGA Embedded Development Suite (SoC EDS) SoC FPGA Software Development Package (Both the Standard Edition and Pro Edition are available in free and paid versions)	●	●	●
cost		free of charge	Paid	Paid
download		download	download	download

note:

*1: You can use the Standard Edition with the Pro Edition license, but you need to install the software separately.
*2: Supported devices differ depending on the version.
・ Correspondence table of Quartus versions and supported devices is here
*3: ^Intel® ^Cyclone® 10 GX uses Pro, but can be used without a license.
*4: Available for Intel ^® Arria ^® 10, Stratix ^® V, Arria ^® V and Cyclone ^® V.
*5: Available for ^Intel® Cyclon ^® V and Stratix ^® V only.
*6: Available for Intel ^® Stratix ^® V, Arria ^® V, and Cyclone ^® V.

Related information

cloud service

Each tool runs on a PC, but cloud services are also available.
There is no need to install or set up tools or libraries, and you can use a machine with the necessary specifications when you need it.

Click here for details

Macnica technical information site

If you have any questions about Quartus ^® Prime, please first refer to Macnica 's technical information site.
We mainly introduce frequently asked questions and information for beginners.

Altima technical information site

MACNICA Forum

User guide

Please refer here for the latest ^Intel® getting started guides, installation guides, handbooks, etc.
If the problem is not resolved on Macnica 's technical information site, please refer to here.

Click here for details (To ^Intel® site)

workshop

Workshops for learning how to use Quartus ^® Prime include free trials and paid training by instructors.
Free online training is available.

Course Name	cost	Overview
^Quartus® Prime Introductory Trial	free of charge	I want to touch Quartus ^® Prime! I want to try it! I want to know the overview! This is a trial (introductory) course for such people. We will pick up key operations from the overall flow and explain them while conducting simple exercises.
^Intel® FPGAs technical training	Paid	A text-based workshop with an ^Intel® Authorized Instructor. We offer a variety of courses to suit your needs.
online training	free of charge	Online training from ^Intel® anywhere, anytime

application note

Click here for the latest technical information related to Quartus ^® Prime.

Click here for details (To ^Intel® site)

License related

Click here for Quartus ^® Prime licensing information.

License type (before purchase)

How to set up a license (after purchase)