explanation

This document describes how to generate timing constraints, circuit configurations that are less prone to failures, and debugging procedures when failures occur.

Target devices include all Intel® FPGA devices, including Stratix® 10, Arria® 10, and Cyclone® 10. It is a document that can be used when the following events occur.

■ Even if the user design has not been changed, the behavior, frequency, and occurrence of bugs differ for each compilation.
■ Inserting the Signal Tap logic analyzer for investigation does not reproduce the failure phenomenon.
■ Failure behavior, frequency, and presence/absence of occurrence differ depending on individual FPGA (P)
■ When the power supply voltage is changed, malfunction operation, frequency, and presence/absence of occurrence differ (V).
■ When the temperature changes, malfunction operation, frequency, and presence/absence of occurrence will differ (fault operation will occur after operating for a certain period of time) (T).
■ Malfunctions start to occur from a certain point (from a certain product lot) (P)
■ Events change when the opposite device is replaced

It has been empirically confirmed that such a phenomenon occurs at a rate of about 80% due to a combination of the following causes.

■ Improperly set timing constraints (e.g. leaked or overwritten timing constraints, disabled by setting False)
■ The circuit configuration does not consider the arrival time difference between signals (one of them is early/late/simultaneous) (e.g. asynchronous reset, distribution of asynchronous signals).
■ Usage outside the conditions specified by timing constraints and timing models (e.g., PVT conditions and input jitter conditions are not met or barely met)

<Contents>

Introduction
Purpose of this document
Checklist
Checkpoint
check flow
Items to check at the right time
Points to note in circuit design
Check clock signal
Checking the power supply voltage
Defect case

Document download