explanation

In Intel® FPGA, through the compilation (logic synthesis, placement, routing) process on the design software (Intel® Quartus® Prime software), data that sets and connects the physical resources in the FPGA is created, and the compilation data is downloaded into the FPGA to implement the required functions as hardware.

In general, FPGAs are manufactured with SRAM-based technology, which does not retain internal data when power is turned off. need to do it. This mechanism is called "configuration", and Intel® FPGA provides several configuration methods.

Despite the fact that the configuration circuit is a relatively simple configuration and is considered a "dead function" as described later, even today, support requests for configuration always account for about 20% of all requests, and Problems such as "configuration fails" occur at a certain rate. This is thought to be due to the following factors.

■ Subtly different circuit configurations and setting methods for each FPGA generation
■ Addition of configuration methods, encryption, remote update, and other functions, resulting in an increase in the volume of user manuals.
■ Increased clock speed to reduce configuration time as FPGA capacity increases

Configuration is performed at the earliest stage, and if it fails, the FPGA will not function, so configuration troubles will have a great impact on the customer's subsequent development process.

This document summarizes points to note in board design, common failure cases, and how to deal with them in the simplest active serial configuration using Quad SPI (QSPI) Flash.

Target devices are Stratix® V, Arria® V, and Cyclone® V.
(There are some differences between earlier families, Intel® Arria® 10 and Intel® Stratix® 10, so be sure to refer to the user manual for each device.)

<Contents>

Introduction
What is configuration
Design guidelines
Debugging guidelines
summary
Appendix

Document