explanation

With Altera FPGAs, the compilation process (logic synthesis, placement, and wiring) on the design software (Quartus® Prime development software) creates data that configures and connects the physical resources within the FPGA, and the required functions are realized as hardware by downloading that compiled data into the FPGA.

Generally, FPGAs are manufactured using SRAM-based technology, and internal data is not retained when the power is turned off, so it is necessary to store the compilation data in an external non-volatile memory and download the compilation data into the FPGA when the power is turned on. This mechanism is called "configuration", and Intel® FPGAs provide several configuration methods.

As we will explain later, configuration circuits have a relatively simple structure and are considered a "mature function." Even today, support requests related to configuration still account for approximately 20% of all requests, and there is a certain percentage of problems such as "configuration failure." The following factors are thought to be the cause of this:

■ Circuit configurations and setting methods vary slightly for each FPGA generation.
■ The user manual has become longer as new features such as configuration methods, encryption, and remote updates have been added.
■ Clock speeds are increasing to shorten configuration times as FPGA capacity increases.

Configuration is performed at the earliest stage, and if it fails the FPGA will not function, so any problems with configuration can have a significant impact on your development process.

This document summarizes the points to be aware of in board design, common problems, and how to deal with them when using the simplest active serial configuration using Quad SPI (QSPI) Flash.

The target devices are Stratix® V, Arria® V, and Cyclone® V.
(There are some differences between previous families, Arria® 10, and Stratix® 10, so be sure to refer to the user manual for each device.)

＜Contents＞

Introduction
What is a configuration?
Design Guidelines
Debugging Guidelines
summary
Appendix

Document