[A-1] Custom MCU design trial

Introducing how to use MAX® 10 FPGA in embedded devices for FPGA beginners that even software engineers can understand.
Using the Odyssey MAX 10 FPGA Eval Kit and MAX 10 FPGA Evaluation Kit developed by our company, you can experience and learn development and application examples in a hands-on format.

[Course fee]

free

[A-2] Nios® II Introductory Trial

This is a hands-on technical seminar for users who are considering introducing Intel's soft-core CPU Nios® II.
The features of Nios® II, the development environment, etc. will be explained, and the basic design method will be learned by actually using the evaluation board and the integrated development environment to learn the basic development flow.

[Course fee]

free

[A-3] Embedded Systems: Nios® II & Platform Designer Basics

Manufacturer-sponsored technical training for users considering the introduction of Intel's soft-core CPU Nios® II.
 

[Course fee]

¥45,000- (excluding tax)

[A-4] SoC Startup Trial

For users who are considering Intel® SoC FPGA development for the first time, we introduce the development flow of Intel® SoC FPGA. This is a hands-on technical seminar where you can experience and learn the actual development flow using Quartus® Prime / Platform Designer and Intel® SoC FPGA Embedded Design Suite.

[Course fee]

free

[A-5] ARM*-based SoC hardware development

Using your existing Platform Designer system design knowledge, we'll show you how to implement an ARM* Cortex*-A9 Hard Processor System (HPS) and an Intel® SoC FPGA. Technical training sponsored by the manufacturer.

<For hardware engineers and firmware engineers>

[Course fee]

¥45,000- (excluding tax)

[A-6] ARM* based SoC software development

Learn about software launch and software development using the ARM* Cortex*-A9 Hard Processor System (HPS) on Intel® SoC FPGA. Technical training sponsored by the manufacturer.

<For firmware engineers and low-level software engineers>

[Course fee]

¥45,000- (excluding tax)

[B-1] Quartus® Prime Introductory Trial

I want to touch Intel® Quartus® Prime! I want to try it! I want to know the overview! This is a hands-on technical seminar for FPGA development beginners.

[Course fee]

free

[B-2] Quartus® Prime Perfect Course I

Use Intel® Quartus® Prime to create a new design, program a device, and learn the basic design flow for Intel® FPGAs. Technical training sponsored by the manufacturer.

[Course fee]

¥45,000- (excluding tax)

[B-3] Quartus® Prime Perfect Course II: Timing Analysis

Learn how to use the Intel® Quartus® Prime Timing Analyzer to set timing constraints on your design and perform timing analysis. Technical training sponsored by the manufacturer.

[Course fee]

¥45,000- (excluding tax)

[C-1] Intel® HLS Introductory Trial

Learn hands-on how to use the Intel® High Level Syntheis (HLS) Compiler to synthesize and verify IP components for ^Intel® FPGAs.

* Intel® HLS Compiler is a high-level synthesis tool that takes C++ as input and generates RTL (Register Transfer Level) code optimized for ^Intel® FPGA.

[Course fee]

free

[C-2] Intel HLS Practical Trial

Introduces performance optimization points for IP component synthesis for ^Intel® FPGAs using the ^Intel® HLS Compiler, focusing on loop and memory access optimizations.

[Course fee]

free

[C-3] Intel® High-Level Synthesis : Optimization

This course teaches you how to use the ^Intel HLS Compiler to create optimized IP for ^Intel FPGAs through real-world design examples. Technical training sponsored by the manufacturer.

[Course fee]

¥45,000- (excluding tax)

[C-4] OpenCL* for Intel® FPGA: Introduction

This course provides an introduction to parallel computing and explores the OpenCL* standard and the structure of the Intel® FPGA development flow that automatically translates kernel C code into hardware that interacts with the host. In the exercises, you will create a program to run in emulation mode using the FPGA board. Technical training sponsored by the manufacturer.

[Course fee]

¥45,000- (excluding tax)

[C-5] OpenCL* for Intel® FPGA: Optimization

This course covers the optimization techniques necessary to implement high-performance OpenCL* solutions on FPGAs. Improve the performance of your OpenCL* kernels using various debugging and analysis tools provided by the Intel® FPGA SDK for OpenCL*. Technical training sponsored by the manufacturer.

[Course fee]

¥45,000- (excluding tax)

Approximate skill level