explanation

Despite its high speed and complexity, PCI Express® (PCIe®) is currently the most popular interface standard in use, but suffers from many levels of problems.

Since it is possible to implement PCIe with various configurations according to the customer's request with FPGA, when unexpected behavior occurs, it becomes difficult to analyze the cause, and it tends to take a long time. . On the other hand, empirically, nearly 80% of our customers have very similar requirements, and unless we need to achieve near-theoretical performance or require a special configuration, we recommend using the same configuration. can cover most customer specifications.

In this document, the above "Design that implements the minimum functions from the configuration that covers almost 80% of customer requirements" is shown as the Golden Reference Design. In addition, the Design Flow and Debug Flow using it are shown to prevent problems from being mixed in by designing in an appropriate procedure, and to quickly solve problems by implementing the mechanism necessary for debugging. It is intended to

This document assumes the use of PCIe hard IP with Arria® 10, but it can also be applied to Stratix® V, Arria® V, and Cyclone® V with some exceptions.

<Contents>

Introduction
Design flow
Debug Flow
lastly
Appendix
Link Up Fail Symptoms and Items to Check
others

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