Altera® FPGA Development Flow Diagram

Altera® FPGA development proceeds as shown in the diagram below. To jump to each development phase, click the corresponding number.

(Click the appropriate number to jump to each development phase.)
 1. Preparation
Download / Install / License setup
 2. Examination of functional specifications
FPGA selection / configuration / power supply & power consumption estimation / board simulation
 3. Logic circuit design
IP Information / Nios® II Information / SoC FPGA Information / OpenCL™ Information
Information on High Level Synthesis (HLS) / New to HDL design
 4. Logical simulation
 5. Constraint setting
 6. Compile
 7. Timing Verification
 8. Programming
 9. Actual equipment verification
10. Mass production

1. Preparation

download

For information on downloading the tool, please see the following page.
▶ How to download Quartus® Prime development software and Questa* - Altera® FPGA Edition

install

After downloading the installation file (installer) for the tool you want to install, the next step is installation.

For instructions on installing each tool, please see here. (If you are using the Nios® II embedded processor, you will also need the Nios® II Software Build Tool (Nios® II SBT), but the Nios® II SBT will be installed automatically at the same time as the Quartus® Prime installation.)

▶ How to install Quartus® Prime development software and Questa* - Altera® FPGA Edition
▶ Altera® SoC FPGA Embedded Development Suite (SoC EDS) Installation Instructions ver.20.1
▶ How to install the Software Development Kit (SDK) for OpenCL™

License settings

Once you have installed the tools, get and set up your license file. (The free-to-use Quartus® Prime Lite Edition can be used without obtaining and setting up a license file.)

License file generation and renewal are performed by signing in to the Altera® website and accessing a dedicated site called the Altera FPGA Self-Service License Center.

　

■ For sign-in, see the information below.

▶ How to create a new Altera® account

▶ How to register for the Altera® FPGA Self-Service Licensing Center

　

■ See below for information on how to obtain a license file.

▶ How to obtain new licenses for Quartus® Prime, IP, and Questa* - Altera® FPGA Edition
▶ How to obtain Quartus® Prime, IP, and Questa* - Altera® FPGA Edition licenses during maintenance renewal.
▶ How to change the NIC ID (Host ID) associated with Quartus® Prime, IP, and Questa* - Altera® FPGA Edition licenses.
▶ How to issue (reissue) license files for Quartus® Prime, IP, and Questa* - Altera® FPGA Edition licenses with assigned NIC IDs.
▶ How to obtain and configure the Questa* - Altera® FPGA Starter Edition license file.

▶ How to obtain a license file for the Nios® V processor IP

　

■ See the information below for setting up the license file.

The license for Altera® FPGAs includes FIXED License and FLOAT License There are two types, but the setup method for each is different.
▶ Quartus® Prime licensing options
▶ How to configure fixed licenses for Quartus® Prime, IP, and Questa* - Altera® FPGA Edition
▶ How to configure FLOAT licensing for Quartus® Prime, IP, and Questa* - Altera® FPGA Edition
▶ How to configure the license for Arm® Development Studio (DS) for Altera® SoC FPGA Edition

 

 ▲ Return to Altera® FPGA development flow chart

2. Examination of functional specifications

Consider the specifications of the functions to be implemented in FPGA / CPLD, and create block diagrams and specifications. By doing some paperwork and using Quartus® Prime to create a simple design (digital logic circuit), we thoroughly consider whether the functionality we want to implement is feasible.

In addition, in order to build a highly reliable logic circuit, it is important to learn the basics of design techniques, which are key points in RTL design of FPGA / CPLD. Before designing a logic circuit, we will introduce articles that FPGA / CPLD users must see. (Since it is easy to impose timing constraints, we recommend synchronous design especially for FPGA/CPLD. Regarding timing constraints, 5. Constraint setting Please refer to the. )

[A Must-See for Beginners in RTL Design] Series Articles
▶ [A must-see for RTL design beginners] Differences between synchronous and asynchronous design
▶ [Must-see for Beginners in RTL Design] Impact on the System when Inputting Asynchronous Signals
▶ [A Must-See for RTL Design Beginners] Effects of Hazard Signals on Systems

Now, I would like to introduce some materials and articles that I would like you to check in advance before proceeding with the specific consideration of FPGA.

3. Logic circuit design

Quartus® Prime supports design in hardware description languages (HDL) such as Verilog HDL, SystemVerilog, and VHDL, as well as schematic design. Quartus® Prime also allows mixing HDL and schematics in the same project.

To begin FPGA/CPLD development with Quartus® Prime, you must first create a project. After creating the project, we will create the design (digital logic circuit) in HDL and circuit diagrams, but if you want to design in circuit diagrams, please refer to the following materials.

Getting Started with Quartus® - Material for Beginners
▶ Quartus® Prime - How to create a project
▶ Quartus® Prime - Using the Schematic Editor

Quartus® Step-Up Guide - Material for Intermediate Users
▶ Quartus® Prime - Managing Projects
▶ Quartus® Prime - Device Migration
▶ Quartus® Prime - Using the Qsys System Integration Tool

* Qsys from Quartus Prime v17.1 Platform Designer has been renamed to

4. Logical simulation

Once the design is complete, logical verification is performed using logic simulation. The simulation uses an RTL simulator such as ModelSim® - Altera® FPGA Edition, but the schematics supported by Quartus® Prime are not supported by RTL simulators. For instructions on converting Quartus® Prime schematics to HDL, please refer to "Quartus® Prime - Using the Schematic Editor".
　

▶ Altera® FPGA Functional Simulation with NativeLink (Standard Edition, Lite Edition)

▶ How to perform function simulation on a design containing IP generated with Quartus® Prime Pro Edition using Questa* - Altera® FPGA Edition (for Pro Edition)

　
<Quartus®Getting Started Guide> -Materials for beginner users​
▶ ModelSim® - Altera® FPGA Edition - RTL Simulation Method

5. Constraint setting

After the RTL simulation is finished, pinouts, device settings, and various constraints are applied. Before compiling, be sure to make the necessary settings and constraints.

<Quartus® Beginner's Guide>-BeginnerMaterials for users
▶ Quartus® Prime - How to set device options
▶ Quartus® Prime - How to make pin assignments
▶ Quartus® Prime - Timing Constraint Methods

<Quartus® Step-up Guide>- IntermediateA user materials for
▶ Quartus® Prime - How to set up the EDA tool
▶ Quartus® Prime - Constraint Method (Assignment Editor)
▶ Quartus® Prime - How to set common pin options

▲ Return to Altera® FPGA development flow chart

6. Compile

After completing various settings and constraints, compile. Full compilation performs logic synthesis, placement and routing, timing analysis, and creation of programming files. After compiling, be sure to check the compilation report.

<Quartus® Beginner's Guide>-BeginnerA user materials for
▶ Quartus® Prime - How to read the compilation report file

<Quartus® Step-up Guide>-Materials for intermediate users

▶ Using Quartus® Prime - Design Space Explorer II

▲ Return to Altera® FPGA development flow chart

7. Timing Verification

Check the timing analysis results at the same time as the compilation report. Timing analysis results on the compilation report are summary information only, use the TimeQuest Timing Analyzer to see detailed results.

<Quartus® Beginner's Guide>-BeginnerA user materials for
▶ Quartus® Prime - How to do Timing Analysis

< FPGA guidelines＞
▶ Timing & Implementation Design & Debug Guidelines/FPGA Guidelines

▲ Return to Altera® FPGA development flow chart

8. Programming

At this point, you will be ready to debug on the actual device. To write data to the FPGA/CPLD or configuration device, launch the Quartus® Prime Programmer and write to the device via an Altera® FPGA download cable (such as USB-Blaster™ II or USB-Blaster™).

＜Quartus® Beginner's Guide > Beginneruser Materials for
▶ Quartus® Prime - How to Program Devices

<Quartus® Step-up Guide＞- Intermediateuser Materials for
▶ Quartus® Prime - Generate and Convert Programming Files

＜For those who want to know more＞
▶ Programming EPCQ devices via FPGA (JIC programming)
▶ Installing the USB-Blaster™ II driver
▶ Installing the USB-Blaster™ driver
▶ Change the TCK frequency of the USB-Blaster™ II

▲ Return to Altera® FPGA development flow chart

9. Actual equipment verification

If the evaluation board is powered on again and the data is successfully transferred from the configuration device to the FPGA, it enters the phase of verifying the operation of the FPGA.

Getting Started with Quartus® - Material for Beginners
▶ Using the Quartus® Prime - Signal Tap Logic Analyzer

<Those who want to know more>
▶ Let's try FPGA on-chip debugging "Signal Tap"

* SignalTap®II from Quartus Prime v17.1 Signal Tap has been renamed to

 ▲ Return to Altera® FPGA development flow chart

10. Mass production

Once the actual machine verification is completed, we can move to mass production.

 ▲ Return to Altera® FPGA development flow chart

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