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This document provides an easy-to-understand introduction to ModelSim® - Altera® FPGA Edition, available for Altera® FPGA users, for first-time users.
For more information on FPGA/CPLD development flow, please see here.
explanation
This document is useful for the "4. Logic Simulation" phase of FPGA/CPLD development.
This tutorial explains how to use ModelSim® - Altera® FPGA Edition to simulate and verify the operation of logic circuits.
To perform logic simulation before logic synthesis (RTL simulation), use a simulator for the hardware description language (HDL), such as ModelSim® - Altera® FPGA Edition.
Document
ModelSim-Altera RTL Simulation Methods
Tool version: Documentation for Ver.15.1 (ModelSim-Altera 10.4b)