This is an introductory course for customers who want to try out Quartus® Prime and get an overview of it.

We will quickly pick out key operations from the overall flow and explain them through simple exercises.

In the exercises conducted during the lectures, VerilogHDL and VHDL designs are prepared in advance. Students will choose one of the designs and proceed with the exercises.

・Altera® FPGA Product Introduction

How to get and install the tool

Quartus® Prime Overview

・ Basic operations

- Project creation / Design creation / Function simulation ^* / Pin assignment settings / Compilation / Programming / Signal Tap (experience)

★ Practice using development board

<Notes>

✔ The simulator tool used is Questa-Altera® FPGA Edition. (If participants bring their own PCs, Questa-Altera® FPGA Starter Edition is also acceptable.)

✔ Timing constraints and analysis are omitted. If you would like to take these courses, please take a separate course or online seminar.

Approximately 4 hours (Example: 13:30-17:30)

can be

Inquiry

In the "Please state the name of the event or seminar you would like to ask about" section, please state "Quartus Prime Introduction course."

In the section titled "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time when you would like the training to take place (e.g. mid-month).

If you're new to FPGAs and Quartus® Prime, but want to learn everything at once, this is the course for you!
(This course is intended for those with a basic understanding of VHDL and Verilog-HDL.)

<First session>
[Part 1] Learn what kind of device an FPGA is, its features, and an overview of the development flow.

*Part 1 can be omitted. The course fee remains the same even if you omit it.

[Part 2] Learn how to use Quartus® Prime. The design used in the exercises will be created in HDL. You will learn how to set options that take advantage of FPGA characteristics, how to set I/O placement, FPGA clock networks and I/O functions, timing constraints, and how to use the Timing Analyzer required for analysis. After compilation, you will learn how to read the report and how to use the Timing Analyzer required for timing analysis. (Continued in Part 2)

<2nd session>
(Continuation of the first exercise)
Program the design in the exercise onto an actual development board and check its operation. Experience the on-chip debugging feature Signal Tap.
In addition, we will also conduct exercises that make use of the features of FPGAs.

・ Basic knowledge of FPGAs (overview / recommendations for synchronous design) *This chapter can be omitted. The course fee will remain the same even if you omit it.

・ Introduction of Altera® FPGA products

- Quartus® Prime feature overview

Basic method

- Project creation / Design input / Logic simulation ^* / Setting constraints / Compilation / Timing verification

/ Programming / On-chip debugging (Signal Probe, Signal Tap)

★ Practice using development board

<Notes>

✔ The simulator tool used is Questa-Altera® FPGA Edition. (If participants bring their own PCs, Questa-Altera® FPGA Starter Edition is also acceptable.)

can be

In the section "Please state the name of the event or seminar you would like to ask about," please state "Altera FPGADesign Basics Course."

In the section titled "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time when you would like the training to take place (e.g. mid-month).

If you're a beginner to FPGAs, VHDL, and Quartus® Prime, but want to learn everything at once, this is the course for you!

<First session>

[Part 1] Learn what kind of device an FPGA is, its features, and an overview of the development flow.

*Part 1 can be omitted. The course fee remains the same even if you omit it.

[Part 2] We will implement the contents of the VHDL Basic Course. (The exercises will be simulation only. The actual exercises will be held on the third day.)

<2nd session>

You will learn how to operate Quartus® Prime. The design used in the exercise will be created in VHDL using what you learned on the first day. You will also learn how to set options that take advantage of FPGA characteristics, how to set I/O placement, and FPGA clock networks and I/O functions. You will learn how to operate the Timing Analyzer, which is necessary for timing constraints and analysis. Finally, you will program the design used in the exercise on an actual development board and check its operation.

<3rd session>

[Part 1] Experience the Signal Tap on-chip debugging feature included in Quartus® Prime.

[Part 2] <2-day comprehensive exercise> Learn how to write VHDL with consideration for optimizing resources and performance. Also, run the design created in the first exercise on a development board. In addition, we will also do exercises that make use of the features of FPGA.

・ FPGA basics (overview / synchronous design recommendations) * This chapter can be omitted. The course fee remains the same even if you omit it.

・Altera FPGA product introduction

・ VHDL Basics

- Overview / Basic structure / Circuit description (simple combinational circuit / complex combinational circuit / sequential circuit / calling lower blocks)

- Exercises

Quartus Prime Overview

- Basic operations of Quartus Prime

- Project creation / Design input / Logic simulation ^* / Setting constraints / Compilation / Timing verification

/ Programming / On-chip debugging (Signal Probe, Signal Tap)

- Practice using the development board

・ Comprehensive Exercise (VHDL description for optimizing design / Utilizing FPGA features)

<Notes>

✔ The simulator tool used is Questa-Altera® FPGA Edition. (If you are using your own PC, Questa-Altera® FPGA Starter Edition is also acceptable.)

Lecture time

Total of 3 sessions (each session lasts approximately 6-7 hours)

Example 1: 3 consecutive days

Example 2: Every Monday (3 weeks in total)

Try it!

can be

In the section "Please state the name of the event or seminar you would like to ask about," please state "Altera FPGADesign Basics Course with VHDL Basics."

In the section titled "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time when you would like the training to take place (e.g. mid-month).

This article introduces the on-chip debugging features of Quartus® Prime, which can be used in various situations during development of Altera® FPGAs.

・ On-chip debugging tools included with Quartus® Prime

- Signal Tap Logic Analyzer / In-System Source and Probe / In System Memory Content Editor / System Console etc.

- Transceiver Channel Evaluation Tool Transceiver Toolkit

External Memory Interface Debug Toolkit

Approximately 3 hours (Example: 13:30-16:30)

none

Inquiry

In the "Please write the name of the event or seminar you would like to ask about" field, please write "Quartus Prime AdvancedCourse (Debug Tools Edition)".

In the section titled "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time when you would like the training to take place (e.g. mid-month).

This course is aimed at customers who are considering introducing Nios® V, a soft-core processor that can be mounted on Altera® FPGAs.
This course will explain the features of Nios® V and the development environment, and will also teach basic design techniques using an evaluation board and integrated development environment, as well as the basic development flow.

What is Nios® V?

- Migration from Nios® II

Nios® V hardware development

Nios® V software development

- Nios® V boot method

★ Exercises using development boards: Platform Designer system creation / hardware design creation / software design creation / software design execution

Approximately 4 hours (Example: 13:30-17:30)

can be

inquiry

In the section titled "Please state the name of the event or seminar you would like to ask about," please specify "Nios V Processor IntroductionCourse."

In the section titled "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time when you would like the training to take place (e.g. mid-month).

Taking advantage of the low-cost, highly efficient features of Agilex™ 3, participants will learn embedded system design and debugging techniques (using the Signal Tap logic analyzer) step by step.
This hands-on, hands-on course for beginners to intermediate developers explores the FPGA development flow through hands-on exercises using the Nios® V processor.

13:30～17:15

This course is currently open to the public. Please check the dates and venue before applying.

• March 11th (Wed) Shin-Yokohama ⇒Click here to apply
• March 24th (Tue) Shinagawa ⇒Click here to apply

It is also possible to hold the event on dates other than those listed above by gathering five or more people from the same company (same group company) or the same work team (different companies). Please contact us first.

In the "Please enter the name of the event/seminar you would like to ask about" section, please specify "Getting Started with FPGA Development with Agilex 3: Hands-on with Nios V and Quartus Prime!"​

In the section titled "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time when you would like the training to take place (e.g. mid-month).

Leveraging the low-cost, highly efficient Agilex™ 3 FPGA, participants will gain practical experience in implementing AI inference models using the FPGA AI Suite.
We will also explain the basics of AI inference and its basic configuration, and in a hands-on session we will implement inference for handwritten digit recognition on an FPGA using the LeNet model.
You can experience the actual development flow and get a real feel for the appeal and potential of AI implementation using FPGAs.

13:30～17:15

This course is currently open to the public. Please check the dates and venue before applying.

• March 3rd (Tue) Shin-Yokohama venue ⇒Click here to apply
• Wednesday, March 11th Osaka venue ⇒Click here to apply

It is also possible to hold the event on dates other than those listed above by gathering five or more people from the same company (same group company) or the same work team (different companies). Please contact us first.

In the "Please enter the name of the event/seminar you would like to ask about" field, please specify "Getting started with FPGA development with Agilex 3: FPGA AI Suite in practice!"​

In the "Please enter the date and time of the event/seminar you would like to inquire about" field, please enter the desired time period for the training (e.g., mid-XX).

This seminar will provide an overview of the device, development environment, and development flow for customers considering Agilex™ 5 SoC FPGA development.

Click here for an overview.

Approximately 4 hours (Example: 13:30-17:30)

5 people or more

*Currently, we are not holding regular events. Please apply by recruiting participants from the same company (including affiliated companies).

In the section "Please specify the name of the event/seminar you would like to ask about," please specify Agilex 5 SoC FPGAHands-on Seminar.

In the section "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time you would like the training to take place (e.g., mid-XX).

This course is aimed at customers who are new to digital logic circuit design using VHDL or Verilog-HDL.

You will get an overview of the language and learn basic writing techniques through simple exercises.

In this exercise, you will perform functional simulation of the code you created using Questa-Altera FPGA Edition.

<VHDL>

・ Language design overview

・ VHDL Fundamentals

・ VHDL Structure

・ Circuit description (simple combinational circuits / simple sequential circuits)

★ Exercises

<Verilog-HDL>

・ Language design overview

・ Verilog-HDL Basics

・ Verilog-HDL Structure

・ Circuit description (assign statement / always statement)

★ Exercises

Approximately 3.5 hours (Example: 13:30-17:00)

can be

Inquiry

In the section "Please enter the name of the event or seminar you would like to ask about," VHDLIntroductioncourse  or Introduction to Verilog HDLcourse Please state this clearly.

In the section titled "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time when you would like the training to take place (e.g. mid-month).

In addition to the content of the [Introduction to VHDL Course], you will learn how to write calls to lower-level entities required for state machines and hierarchical design.
In this exercise, you will perform functional simulation of the created code using Questa-Altera FPGA Edition, and also check its operation on a real device using Quartus Prime and an evaluation board.

- Language design overview

・Basic structure of VHDL

Circuit description

- Simple combinational circuits

- Complex combinational circuits

- Sequential Circuits

- Calling lower blocks

★ Practice using development board

Approximately 6 hours (Example: 10:00-17:00)

can be

Inquiry

In the section "Please enter the name of the event or seminar you would like to ask about," VHDL Basic Course  Please state this clearly.

In the section titled "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time when you would like the training to take place (e.g. mid-month).

Achieving maximum performance from the Hyperflex® architecture requires architectural knowledge and RTL design technique.

This course will teach you the techniques and design methods.

This product is recommended for users considering new designs with Agilex™ 7/Agilex 5™, or for users considering migrating from the Cyclone® series or Arria® series to the Agilex™ series.

none

In the section titled "Please specify the name of the event/seminar you would like to ask about," please specify Hyperflex Architecture Design Techniques course.

In the section titled "Please enter the date and time of the event/seminar you would like to inquire about," please enter the time when you would like the training to take place (e.g. mid-month).