Purpose of this course

Overview

In this seminar, you will learn about the overview and operation flow of the Quartus® Prime  development software, which is required when developing Altera® FPGAs.

We also publish the exercise manual and exercise data as hands-on.

If you use the development board during the exercise, you can experience the exercise while operating it on the actual machine.

(Some exercises can be performed without a development board.)

Target Audience
・People who want to get a rough overview of the FPGA development flow
・People who are just starting or considering Altera® FPGA development
- First time users of Quartus® Prime
- People who are already developing FPGAs but want to review the basic operations of Quartus® Prime
　  

goal of attending

Learn how to install Quartus® Prime
- How to download, install, and obtain and set up a license file

・Know the overall flow of FPGA development

・Learn the basic operations of Quartus® Prime

・Hands-on experience with Quartus® Prime (only for users who have completed the exercises)

agenda

1. Altera® FPGA Product Introduction
2. Download and Install Quartus® Prime
3. Obtaining and setting the license file
4. Quartus® Prime Overview
5. Basic Operations with Quartus® Prime

Altera® FPGA Product Introduction

This chapter introduces the Altera® FPGA device family.

(Duration: 4 minutes 00 seconds)

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Download and Install Quartus® Prime

This chapter describes how to download and install Quartus® Prime.

(Duration: 6 minutes 22 seconds)

 

[Content introduced in this chapter]

​How to download Quartus® Prime and Questa* - Altera® FPGA Edition

​How to install Quartus® Prime and Questa* - Altera® FPGA Edition

・ Quartus® Prime Supported Device List

・ Quartus® Prime Supported OS Compatibility Table

・FPGA Operating System (OS) Support

​How to register for an Intel account

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Obtaining and setting the license file

This chapter introduces how to obtain and configure a license file.

(Duration: 2 minutes 30 seconds)

 

 

[Content introduced in this chapter]

​How to get a new license for Quartus® Prime, IP and Questa* - Altera® FPGA Edition

​How to set up FIXED licenses for Quartus® Prime, IP and Questa* - Altera® FPGA Edition

​How to set up FLOAT licenses for Quartus® Prime, IP and Questa* - Altera® FPGA Edition

・ Quartus® Prime license format

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Quartus® Prime Overview

This chapter provides an overview of what kind of development software (tool) Quartus® Prime is and explains the basic operation flow.

(Duration: 3 minutes 27 seconds)

 

[Content introduced in this chapter]

・ Altera® FPGA development flow

・ Let's try FPGA on-chip debugging “Signal Tap”

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Basic Operations with Quartus® Prime

This chapter introduces the following operations flow for Quartus® Prime:

Please scroll the screen to the chapter you want to see.

 

・Creating a project

・Design creation

・Logic simulation

・Constraint setting (pin layout etc.)

·compile

・Timing verification

·programming

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Create a project

This chapter introduces how to create a new project.

(Duration: 2 minutes 20 seconds)

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Create a design

This chapter describes the design entry methods supported by Quartus® Prime, as well as the Analysis & Elaboration and Message windows.

(Duration: 5 minutes 52 seconds)

 

[Content introduced in this chapter]

・ Let's try it for the first time! VHDL <with exercises>

・ Let's try it for the first time! Verilog HDL <with exercises>

・FPGA のサンプル・デザインを無料で手に入れよう

 

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Logical simulation

This chapter describes functional simulation using Modelsim® - Altera® FPGA Edition.

(Required time: 6 minutes 06 seconds)

 

[Content introduced in this chapter]

・ Let's try it for the first time! Test bench

​ModelSim® - Altera® FPGA Edition - RTL Simulation Method

・ Use NativeLink to solve Altera® FPGA functional simulation

​How to functionally simulate a design containing IP generated with Quartus® Prime Pro Edition in Questa* - Altera® FPGA Edition

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Constraint setting (pinout etc.)

In this chapter, we will introduce typical constraints that are performed before compilation.

(Duration: 8 minutes 47 seconds)

 

・Pin assignment and I/O standard setting

・Set unused user I/O pins

・Configuration settings

・Other option settings

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compile

This chapter introduces how to compile and the reports that are generated.

(Duration: 3 minutes 13 seconds)

 

・Compile execution

・Compile report

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timing verification

This chapter introduces timing verification.

(Duration: 3 minutes 09 seconds)

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programming

This chapter introduces programming.

(Duration: 4 minutes 51 seconds)

 

[Content introduced in this chapter]

・ Programming to EPCQ device via FPGA (JIC programming)

・ Install the USB-Blaster II driver

・ Install the USB-Blaster driver

・ Try changing the TCK frequency of the USB-Blaster II

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Actual machine verification

This chapter introduces you to the Signal Tap logic analyzer.

(Duration: 2 minutes 25 seconds)

 

[Content introduced in this chapter]

・ Let's try FPGA on-chip debugging “Signal Tap”

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practice content

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