1. IOPLL Generation

Here, Cyclone® 10 GX project is used as an example.

Open a project whose target device is Cyclone® 10 GX or create a new project.

(For Quartus® Prime project creation, refer to Quartus® Getting Started Guide - How to Create a Project.)

Type pll into the IP Catalog search bar within Quartus® Prime.

Then you can easily find the IOPLL.

​With IOPLL highlighted, click Add.

IP Parameter Editor launches.

Specify the folder path where you want to create the IOPLL and the name you want to give to the IOPLL, then click Create.

It is recommended that the IP be generated in the working folder of the project or a folder below it.

The IOPLL parameter setting window will launch.

If you want to see detailed documentation and explanations of each setting item here, click the Details tab.

This section provides an overview of the main setting items on each tab.

PLL tab

Configure general settings such as reference clock (input clock) frequency, locked pin enable/disable, number of output clocks, and output clock settings.

Here, as an example, the settings are set as shown in the table below.

Reference clock frequency	50 (MHz)
Enable locked output port	✔ (On)
Compensation Mode	direct

Number Of Clocks	2
outclk0
Desired frequency	100 (MHz)
Desired Pahse Shift	0 (ps)
Desired Duty Cycle	50 (%)
outclk1
Desired frequency	100 (MHz)
Desired Pahse Shift	90 (degrees)
Desired Duty Cycle	50 (%)

Settings tab

Configure PLL bandwidth preset, Clock Switchover (function to switch between two inputs), LVDS External PLL, and external clock output.

To output the clock generated by the PLL to the outside of the FPGA, output from a dedicated port is recommended. Make settings for that.

 

The other tabs allow you to set the following parameters. For more information, see the IOPLL user guide.

Advanced Parameters Tab

You can see the PLL parameter names and parameter values, such as the PLL M/N/C counter value and VCO frequency.

 

 

 

After setting various parameters, save the settings by selecting File menu ⇒ Save in IP Parameter Editor Pro.

Click Generate HDL on the bottom right to display a screen for selecting the HDL language to generate.

The Synthesis section selects the language of the files Quartus Prime uses for logic synthesis.

In the Simulation section, select the simulation model language for the EDA simulator.

Click Generate to generate the IP.

Close the IP Parameter Editor.

Now that the IOPLL generation is complete, you can connect it to your own circuit and proceed with the logic design.

If you want to change the IOPLL parameter settings, please see this FAQ.

[FAQ] How to launch the IP editing screen

After editing the necessary parts, generate the IOPLL again.

2. Connection with user circuit

Once the IOPLL is generated, connect it to the user logic.

If you are not familiar with Verilog-HDL or VHDL, please refer here. See Calling Subordinate Modules (Blocks) within this page.

Let's start! Verilog-HDL <with exercises>
Let's start! VHDL <with exercises>

If you are designing with a schematic (circuit diagram), you can not simulate it as it is, so we recommend that you design with HDL.

(* Pro Edition does not have the function to convert schematic files to HDL.)

3. Check by simulation

Let's check the behavior in simulation.

This time we will use ModelSim® - Altera® FPGA Edition.

A testbench is required for verification in simulation, but the testbench is created by the user.

See here for instructions on how to create a testbench.

Let's start! Test bench

Once you have your testbench, you are ready to simulate!

You can manually navigate and simulate with ModelSim®, but here is a convenient method. please refer.