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table of contents
This article introduces the most commonly referenced manufacturer documents for users considering and using Microchip FPGAs (formerly Microsemi and Actel).
We have put together our company information and FAQs.
1. About Microchip FPGAs
2. Device Family
3. Development Kit
4. Where to find Microchip FPGA documentation
5. Macnica developed software, license related documents
6. Reference materials for first-time PolarFire users
7. Reference materials for first-time users of Libero SoC
8. IP
9. Mi-V RISC-V Processor
10. MIPI
11. CoaXPress
12. Edge AI Solutions
13. TCL
14. Other (About Microchip University, Obtaining PCN Information)
Macnica FPGA FAQ List
inquiry
The information below may become outdated due to new documents or changes to the links. Please refer to the latest manufacturer documents.
・Please go to the desired item from the list of items on the left or the links at the top. Or, please use Ctrl + F to search for words on the page. (Power supply, I/O Editor, CCC, etc.)
- Click the round purple up arrow button displayed under Accessibility on the right side of the page to return to the top of the page.
1. About Microchip FPGAs
| Document | URLs | remarks | Classification | |
| Microchip University |
Hello FPGA |
URL | *Please register for a myMicrochip account. | Microchip |
| Features of Microchip's non-volatile FPGA | Three distinctive advantages of non-volatile FPGAs | URL | MACNICA site: Article | |
| Low Power Consumption [Part 1] Why low power consumption? | URL | MACNICA site: Article | ||
| Low power consumption [Part 2] Measuring power consumption/temperature! | URL | MACNICA site: Articles/videos/materials | ||
| Soft Error (SEU) Resistance [Part 1] Why is it resistant to soft errors? | URL | MACNICA site: Article | ||
| Soft Error (SEU) Tolerance [Part 2] Differences between FlashROM and Flash-based FPGA | URL | MACNICA site: Article | ||
| Space saving edition | URL | MACNICA site: Article | ||
2. Device Family
| Item | Document | URLs | remarks | Classification |
| Product catalog | FPGA and SoC Product Families | URL | Microchip | |
| Device Family Introduction | PolarFire | URL | MACNICA site: Article | |
| PolarFire SoC | URL | MACNICA site: Article | ||
| IGLOO2 | URL | MACNICA site: Article | ||
| SmartFusion2 | URL | MACNICA site: Article | ||
| IGLOO | URL | MACNICA site: Article | ||
| ProASIC3 | URL | MACNICA site: Article | ||
| Device selection: Confirm Microchip FPGA equivalent to Altera (formerly Intel), AMD (formerly Xilinx), Lattice, Efinix, Gowin | FPGA Selector Guide | URL | Scroll down the page and click Download FPGA Selector in the Find the Best PolarFire FPGA or SoC for You section to download MCHP_FPGA_Cross_Reference.xlsm. | Microchip |
3. Development Kit
4. Where to find Microchip FPGA documentation
Note :
There is a mixture of documents from the time of Microsemi and Microchip. When searching Google, the older documents may come up at the top even if they are the same documents. When searching for the latest version, we recommend accessing the Microchip website instead of searching Google.
To find the documentation, open the device's homepage, scroll down to the section called Documentation.
| Item | Document | URLs | remarks | Classification |
| Documentation Location | Microchip HP | URL | Microchip | |
| Microchip Japanese documentation | URL | Microchip | ||
| Catalog(pdf) | URL | Microchip | ||
| PolarFire Mid-Range FPGAs | URL | Microchip | ||
| PolarFire SoC FPGAs | URL | Microchip | ||
| IGLOO 2 FPGAs | URL | Microchip | ||
| SmartFusion 2 FPGAs | URL | Microchip | ||
| IGLOO FPGAs | URL | Microchip | ||
| SmartFusion FPGAs | URL | Microchip | ||
| ProASIC3 FPGAs | URL | Microchip | ||
| Knowledge Base | URL | Microchip | ||
| forum | URL | Microchip | ||
| Portal | Microchip non-volatile FPGA related portal | URL | MACNICA site: Article | |
| Introduction to Libero SoC | Microchip "Libero SoC Introduction Edition" released in video! | URL | MACNICA site: Articles / Videos / Materials |
5. Macnica developed software, license related documents
| Item | Document | URLs | remarks | Classification |
| development software | Types of Microchip development tools and supported devices | URL | Libero SoC, Libero IDE, Supported Devices, Tool Downloads | MACNICA site: Article |
| Microchip Libero SoC - Supported OS compatible | URL | MACNICA site: Article | ||
| license | Microchip Development Tools License | URL | License list (Evaluation, Silver, Gold, Platinum, Standalone, Archival), License type (Node Locked DiskID, Node Locked MAC ID, Floating MAC ID, Floating HOST ID) | MACNICA site: Article |
| Libero SoC Related Information | Libero SoC Related Information | URL | MACNICA site: Articles/materials | |
| Various setting methods | Pin_assign_v2.0.pdf | URL | How to specify pin assignments using the I/O Editor | MACNICA site: Materials |
| IO_bank_setting_v2.0.pdf | URL | How to set the I/O Standard for each bank of the device | MACNICA site: Materials | |
| IO_Register_v2.0.pdf | URL | How to set I/O Register constraints | MACNICA site: Materials | |
|
FloorPlanning_v1.0.pdf Sample design (compatible with v12.3 and later): floorPlan_v12.3.zip |
How to set Floor Planning constraints | MACNICA site: Materials | ||
| How to use various functions | Archive_project_v2.0.pdf | URL | How to compress a set of development data into a file | MACNICA site: Materials |
| SSN_Analyzer_v2.0.pdf | URL | How to use SSN Analyzer. This function automatically calculates the probability of simultaneous switching noise from the design. | MACNICA site: Materials | |
| Environmental setting | proxy_v2.0.pdf | URL | Libero SoC proxy settings. Settings required to automatically obtain IP catalogs and Libero SoC updates from the Web. | MACNICA site: Materials |
| Tool_profiles_v2.0.pdf | URL | Tool profiles settings. How to set up different versions of Synplify, Modelsim, etc. | MACNICA site: Materials | |
| IP Related | Microchip IP Related Information | URL | MACNICA site: Articles/materials | |
| IP Overview_v2.0.pdf | URL | Overview of IP. You can understand the concepts for using IP such as how to manage IP, download, and environment settings. | MACNICA site: Materials | |
| IP_Component_version_change_v2.0.pdf | URL | How to change IP Component version | MACNICA site: Materials | |
| IP_Component's Import_v2.0.pdf | URL | How to copy an IP Component from an existing project | MACNICA site: Materials |
6. Reference materials for first-time PolarFire users
| Item | Document | URLs | remarks | Classification |
| Model Number (Ordering Information) | PolarFire FPGA Product Overview | URL | The PolarFire FPGA Product Overview is available by scrolling down the device family page and going to the Overviews tab under Documentation. It is also listed under the Product Selector Guide tab. | Microchip |
| Advance power consumption estimation | Microchip power consumption related information | URL | We use the power consumption calculation tool MPE (Microchip Power Estimator) in Excel. Please refer to the Japanese document: MPE_v2021_r1.0.pdf. |
MACNICA site: Articles/materials |
| Basic information about board design | PolarFire FPGA Board Design User Guide | URL | Scroll to the bottom of the page and open the User Guides tab to find the PolarFire FPGA Board Design User Guide. It contains information about power supplies, connections to the JTAG header and SPI Flash, a Board Design Checklist, and more. |
Microchip |
| Banks per Device | PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide | URL | Scroll to the bottom of the page and open the User Guide tab. In the PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide, 3. I/O Banks lists the HSIO Bank and GPIO Bank. | Microchip |
| Number of PLLs | PolarFire FPGA Product Overview | URL | Scroll to the bottom of the page and open the Overviews tab. It is listed in 3. Product Family Table of the PolarFire FPGA Product Overview document. | Microchip |
| Pin List | Package Pin Assignment Table | URL | Scroll to the bottom of the page and open the Data Sheets tab. Obtain the MPFxxxxxx Package Pin Assignment Table file in the Packaging/PPATS section. | Microchip |
| How to handle unused pins on the board | Package Pin Assignment Table | URL | Scroll to the bottom of the page and open the Data Sheets tab. Obtain the MPFxxxxxx Package Pin Assignment Table file in the Packaging/PPATS section. To the right of the pin list, there is an Unused Condition column. | Microchip |
| Power-on sequence | PolarFire FPGA Board Design User Guide | URL | Scroll to the bottom of the page and open the User Guides tab. You will find the I/O Glitch in the PolarFire FPGA Board Design User Guide. | Microchip |
7. Reference materials for first-time users of Libero SoC
| Item | Document | URLs | remarks | Classification |
| Libero SoC Supported OS | Libero SoC Design Suite v<version> Release Notes | URL | You can find the Release Notes by scrolling down to the Libero SoC page and selecting Download Software. Please refer to the System Requirements > Supported Operating Systems section. |
Microchip |
| Libero SoC PC Memory Requirements | Libero SoC Design Suite v<version> Release Notes | URL | You can find the Release Notes by scrolling down to the Libero SoC page and selecting Download Software. Please refer to the System Requirements > System Memory Recommendations section. |
Microchip |
| Get Libero SoC | Libero SoC Design Suite Versions <version> to 12.0 | URL | No login required for download | Microchip |
| Libero SoC installation and licensing | Installing and Licensing Libero SoC | URL | Microchip | |
| Obtaining and setting up licenses | Microchip Development Tools License | URL | A Microchip Account is required. A free Silver license is available. | MACNICA site: Articles/materials |
| Getting Started with Libero SoC | Getting Started Using Libero SoC Design Suite | URL | This is a tutorial for PolarFire FPGA, using the PolarFire Splash Kit (MPF300-SPLASH-KIT-ES) as an example. | Microchip |
| Introduction to Libero SoC | Microchip "Libero SoC Introduction Edition" released in video! | URL | You can check all the operations from obtaining Libero SoC to creating a project, design input, I/O Attributes constraints, simulation, timing constraints, logic synthesis, placement and routing, timing analysis, power consumption analysis, writing (programming), and debugging (Identify, Smart Debug). | MACNICA site: Articles / Videos / Materials |
| Libero SoC Design Flow | Libero SoC Design Flow User Guide Libero SoC v<version> | URL | Scroll down the page and open the User Guides tab in the Documentation section to find documentation for each version. You can get the documentation at Libero SoC Design Suite v<version> Design Flow User Guide for All FPGA Families. This contains explanations about the Libero SoC GUI, such as licenses, project creation, and Archive Project. |
Microchip |
| When creating a new project | Microchip FPGA: regarding the pinout in the I/O Editor. It cannot be assigned to the pin assigned to "DDRIO" in I/O Editor. Actually, I want to use normal LVCMOS2.5V, but only "LVCMOS18" is listed. | URL | When creating a new project, there is a setting item called "Default I/O technology". This is reference information about this pull-down setting. (It can be changed later.) | MACNICA site: FAQ |
| Download IP | Microsemi IP > IP download | URL | Libero SoC's IP is downloaded (so you can use new versions of IP without waiting for the next Libero SoC release). The initial download will take some time, so we recommend that you download it as soon as possible when you have time. * Libero SoC project creation is required to download IP |
MACNICA site: Materials |
| Microchip FPGA: I installed the latest version of Libero SoC, but the library in the "Catalog" tab seems to be missing. I ran "Reload Catalog" but it didn't help. Please let me know if there is a correct procedure. | URL | FAQs for reference when you cannot download IP | MACNICA site: FAQ | |
| Archive Project | Archive Project V2.0 | URL | How to archive the Libero SoC Project (All, Project files only, Source files only) | MACNICA site: Materials |
| Design creation (HDL) | Libero SoC Design Flow User Guide Libero SoC v<version> | URL | Scroll down the page and open the User Guides tab in the Documentation section to find documentation for each version. Please open the Libero SoC Design Suite v<version> Design Flow User Guide for All FPGA Families document and refer to the Designing with HDL section in the Creating and Verifying Designs section. |
Microchip |
| Design creation (circuit diagram) | Libero SoC Design Flow User Guide Libero SoC v<version> | URL | Scroll down the page and open the User Guides tab in the Documentation section to find documentation for each version. Please open the Libero SoC Design Suite v<version> Design Flow User Guide for All FPGA Families document and refer to the Create New SmartDesign section in the Creating and Verifying Designs section. |
Microchip |
| Test bench creation | Libero SoC Design Flow User Guide Libero SoC v<version> | URL | Scroll down the page and open the User Guides tab in the Documentation section to find documentation for each version. Please open the Libero SoC Design Suite v<version> Design Flow User Guide for All FPGA Families document and refer to the Create New SmartDesign section in the Creating and Verifying Designs section. |
Microchip |
| IP | Microsemi IP | URL | Differences in the color of the lock mark in the IP Catalog | MACNICA site: Materials |
| Clock Conditioning Circuitry (CCC) | URL | If you want to use PLL IP on Libero SoC, use the Clock Conditioning Circuitry (CCC) IP. | Microchip | |
| IO Bank Settings | IO_bank_setting_v2.0.pdf | URL | How to set the I/O Standard for each bank of the device | MACNICA site: Materials |
| Pin assignment | Pin_assign_v2.0.pdf | URL | How to specify pin assignments using the I/O Editor | MACNICA site: Materials |
| programming | Microchip Programming Information | URL | Introduction to FlashPro Express, FlashPro, Get Tools, FlashPro6/5/4, FlashPro Lite, Silicon Sculptor 4/3 | MACNICA site: Article |
| debug | Overview of Microchip Debugging Techniques | URL | How to use SmartDebug, SmartDebug Standalone: Overview of SmartDebug Standalone Mode, Identify: How to use Identify (In-circuit Logic Analyser) | MACNICA site: Articles/materials |
8. IP
| Item | Document | URLs | remarks | Classification |
| IP | IP Search | URL | You can search for IP. | Microchip |
| IP Related | Microchip IP Related Information | URL | MACNICA site: Articles/materials | |
| IP Overview_v2.0.pdf | URL | Overview of IP. You can understand the concepts for using IP such as how to manage IP, download, and environment settings. | MACNICA site: Materials | |
| IP_Component_version_change_v2.0.pdf | URL | How to update IP used in Libero SoC projects | MACNICA site: Materials | |
| IP_Component's Import_v2.0.pdf | URL | How to copy an IP Component from an existing project | MACNICA site: Materials |
9. Mi-V RISC-V Processor
10. MIPI
| Item | Document | URLs | remarks | Classification |
| MIPI IP | MIPI CSI2 RxDecoder PF | URL | There are also various other MIPI IPs such as TX and DSI. Each IP can be found from IP Search. | Microchip |
| MIPI | PolarFire FPGA Board Design User Guide | URL | The documentation can be found at the bottom of the page under the Documentation > User Guides tab. There is an item called "1.9 MIPI Hardware Design Guidelines." | Microchip |
| MIPI | PolarFire FPGA and PolarFire SoC FPGA User I/O -Consolidated IOD Rules | URL | The document can be found at the bottom of the page under the Documentation > User Guides tab. Clicking it will download an Excel file called Consolidated_IOD_Rules, which will have a MIPI tab inside. | Microchip |
11. CoaXPress
| Item | Document | URLs | remarks | Classification |
| CoaXPress | CoaXPress IP User Guide | URL | Microchip | |
| AN5021: PolarFire CoaXPress Video Application Note | URL | Microchip | ||
| Features of Microchip's non-volatile FPGA: Low power consumption [Part 2] Measuring power consumption and temperature! | URL | CoaXpress 12.5G power consumption and device temperature measurement | MACNICA site: Articles/videos/materials | |
| CoaXPress PHY | CoaxPress Solution from Microchip | URL | CoaXPress PHY. 12.5Gbps compatible models available. | MACNICA site: Article |
| CoaXPress transceiver "EQCO62T20" capable of transferring up to 68m@6.25Gbps | URL | MACNICA site: Article |
12. Edge AI Solutions
| Item | Document | URLs | remarks | Classification |
| Edge AI solution | Solutions for industrial equipment realized with ultra-low power consumption and high reliability FPGA and SoC FPGA — Industrial Edge: Introduction of AI/Embedded Vision IP, OPC-UA, and Functional Safety Development Kit (Youtube) |
URL | Microchip | |
| Microchip edge AI solution "VectorBlox" | URL | MACNICA site: Article |
13. tcl
| Item | Document | URLs | remarks | Classification |
| tcl | Let's make the most of Microchip's Libero SoC! | URL | MACNICA site: Article |
14. Other (About Microchip University, Obtaining PCN Information)
| Item | Document | URLs | remarks | Classification |
| Microchip University | About Microchip University | URL | MACNICA site: Article | |
| PCN information notification settings | myMicrochip Settings | URL | Log in to myMicrochip from the top right. Open myMicrochip Settings from the top right and set your email notification settings, frequency, and target products from the PCN tab. | Microchip |
| PCN Information | Product Change Notifications | URL | Microchip |
Macnica FPGA FAQ List
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