Agilex™ 7 F-Series FPGAs & SoCs enable 100G Ethernet and more using built-in transceivers.

This video provides a quick introduction to the Agilex™ 7 F-Series FPGA & SoC built-in Ethernet block and useful debug tools.

[Duration] 1 minute 57 seconds / [Video release date]2021/01/21

Introducing the Agilex™ 7 F-Series FPGA & SoC transceivers and the Transceiver Toolkit debug tool.
You can also watch a demonstration of the Transceiver Toolkit using the Agilex™ 7 F-Series FPGA Development Kit.

[Duration] 4 minutes 6 seconds / [Video release date] 2021/02/12

Provides an overview of the Agilex™ 7 F-Series FPGA & SoC transceiver tiles and describes the P-tile transceiver architecture used in the PCI Express protocol.
We will also demonstrate the results of PCIe DMA transfers using the Agilex™ 7 F-series FPGA development kit.

[Duration] 4 minutes 34 seconds / [Video release date]2021/01/26

We will introduce the P-Tile Debug Toolkit, a PCI Express debugging tool for Agilex™ 7 F-series FPGAs & SoCs, and its actual operation at Gen4 (16 Gbps).

We also measured the eye pattern during operation using a differential probe soldered onto the board, so please take a look at the results.

[Duration] 8 minutes 29 seconds / [Video release date] 2021/10/04

We will introduce the results of connection tests between the Agilex™ 7 F-series FPGA development kit and a PCIe Gen4 Rate compatible Desktop PC (Intel® CPU).
We also provide the results of performing DMA transfers using the example design with the Avalon-MM interface configuration.

[Published] 2022/04/01

This video introduces the transceivers built into the Agilex™ 7 I-series FPGA & SoC. This video focuses on the F-tile transceivers, and not only provides an overview but also briefly introduces the transceiver implementation procedure, transceiver performance using the transceiver toolkit, and evaluation results for 400G Ethernet and SDI.

[Duration] 7 minutes 47 seconds / [Video release date] 2022/06/24

We will introduce a demonstration of the PCIe Gen4 x16 Performance Design using the Agilex™ 7 F-series FPGA development kit.
We have also posted the transfer performance results using the highly efficient DMA circuit, so please take a look.

[Published] 2023/06/06

This article introduces a case study on verifying the connection between Agilex™ 7 FPGA and Analog Devices' high-speed A/D converter AD9083 using the F-tile JESD204B IP. The AD9083 is configured using Nios® V.

[Publication date] 2023/11/27

The Agilex™ 7 FPGA & SoC External Memory Interface (EMIF) IP supports the Debug Toolkit for use during debugging.

This video introduces the Agilex™ 7 FPGA & SoC and DDR4 Memory Debug Toolkit.

[Duration] 6 minutes 7 seconds / [Video release date]2021/01/07

The Agilex™ 7 FPGA & SoC External Memory Interface (EMIF) IP supports Traffic Generator 2.0 to test various operations.

In this video, we will explain the setting items of Traffic Generator 2.0 and introduce the test results with demonstrations.

[Duration] 4 minutes 23 seconds / [Video release date]2021/04/02

This article introduces a case where write and read operations were performed from the FPGA-to-HPS Bridge of the Agilex™ 7 FPGA & SoC to DDR4 memory in SDRAM direct mode.

[Published] 2022/09/20

This article describes the DDR4 random address access efficiency measured by changing the settings of the External Memory Interface (EMIF) IP of Agilex™ 7 FPGA & SoC.

[Published] 2023/01/13

Agilex™ 7 F-Series FPGAs & SoCs include more powerful DSP blocks than the previous generation.

This video shows the enhanced DSP block and a quick demo using an example design.

[Duration] 1 minute 37 seconds / [Video release date]2021/01/21

Model-based design can be performed using DSP Builder for Agilex™ 7 FPGA & SoC. This article introduces how vector representation of signals can be used to describe designs in an easy-to-understand and compact manner, and provides an example of designing a floating-point compatible FIR filter.

[Duration] 5 minutes 49 seconds / [Video release date] 2021/06/08

Agilex™ 7 F-series FPGAs and SoCs allow I/O PLL reconfiguration just like traditional Altera® FPGAs.
This video shows you how to reconfigure the I/O PLL using a sample design in the Design Store, along with step-by-step instructions.

[Duration] 9 minutes 27 seconds / [Video release date] 2021/06/08

Agilex™ 7 FPGAs and SoCs can also perform partial reconfiguration, just like traditional Altera® FPGAs.
This video provides an overview of partial reconfiguration and shows how to perform partial reconfiguration using a sample design provided by Altera®.

[Duration] 19 minutes 27 seconds / [Video release date] 2022/01/11

Agilex™ 7 FPGAs and SoCs support Remote System Update (RSU), which allows you to selectively update configuration data.
This video introduces the basic operation of RSU and actual operation procedures using sample designs in the Design Store.

[Duration] 19 minutes 25 seconds / [Video release date] 2022/01/12