​^Intel 's unique 3D heterogeneous system-in-package Agilex™ is an embedded multi-die interconnect bridge that includes FPGA core fabric, hard memory controller, HPS, encryption block, and high-speed transceiver block (EMIB) connected configuration.

The block (die) framed in red that incorporates this high-speed transceiver and various hard IPs is the tile. There are several types of tiles depending on the bandwidth of the transceiver, the type of embedded hard IP, etc. In addition, ^Intel® Agilex™ FPGAs have different types and combinations of tiles depending on the series such as F/I/M, logic scale, and package type.

Agilex™ FPGA tiles are divided into E-tiles, F-tiles, P-tiles, and R-tiles, depending on transceiver specifications and hardware IP installed to support various protocols.

The main features and maximum specifications of each tile are shown in the table, but the performance of each tile is not uniform. 3) have different supported functions and performance.

This table shows the type and number of tiles mounted for the F-series and I-series logic sizes and packages of Agilex™ FPGAs.

The following figure shows the logic size framed in red and the configuration of the device tiles in the package.

The device tile framed in red in the previous table has two F tiles, so the device configuration is as shown in this figure.

It is a device that has a main logic die described as Hyperflex and two F-tile transceiver dies in one package.

Using the F-tile as an example, we will introduce the bandwidth and speed grade correspondence of each transceiver.

The F-Tile has two types of transceivers: a general-purpose transceiver called FGT and a high-speed transceiver called FHT. The bands supported by FHT and FGT transceivers depend on the speed grade of the transceiver and are specified in the datasheet.

This table shows the type and number of tiles mounted for the logic scale and package of the F-series and I-series of Agilex™ FPGAs.

The logic size framed in red and the configuration of the device tiles in the package are shown in the following figure.

The device tile framed in red in the previous table has two F tiles, so the device configuration is as shown in this figure.

The device has a main logic die, described as Hyperflex, two E-tile transceiver dies, and one P-tile in a single package.

Here, we will use the E-tile as an example to introduce the bandwidth and speed grade correspondence of each transceiver.

The bands supported by F-tile transceivers depend on the speed grade of the transceiver and are specified in the datasheet.