TTL provision

The first practical logic ICs were the 74 series TTLs developed in the early 1960s. At first, gates were the main focus, but later small-scale combinational circuits, such as decoders and multiplexers, and sequential circuits such as counters and shift registers, were announced. Small-scale gates were called SSI (Small Scale Integration), and as the degree of integration increased, they were called MSI (Medium Scale Integration) and LSI (Large Scale Integration). After that, VLSI (Very Large Scale Integration) and ULSI (Ultra-Large Scale Integration) followed, but it seems that such a distinction disappeared at some point.

At that time, logic was built with SSI, so there were regulations about how many loads could be connected to one output. Figure 1 is a schematic of a TTL. Unlike CMOS, input current must be considered. With a maximum of 1.6 mA per pin, if the driver had a drive capability of 16 mA, I could only connect 10 loads to one output. This 1.6 mA load is called a Fan-In of 1. Since the output can flow 16 mA, the fan-out is called 10. Since the input capacitance of TTL was about 1.5 pF, connecting 10 will result in 15 pF.

The delay time measurement condition for the 74 series was a load capacitance CL = 15 pF, but for the next high-speed 74S series, this specification was changed to 50 pF. The reason why it became 50 pF is a matter of speculation, but the fan-in of the low power version of the 74S, the 74LS series, was 0.25, and the fan-out of the 74S was 12.5. I think that it was necessary to stipulate a large capacity in order to be able to connect the 74LS.

Lumped-constant thinking

As mentioned in "Boundary Line between Distributed Constant Circuit and Lumped Constant Circuit", the boundary between lumped constant and distributed constant is the point where the rise time of the signal and the round trip time of the line are exceeded. TTL drivers have slow rise times, for example 10 ns. Since the wiring length is about 20 cm at the longest, the round trip time of the line is about 3 ns, that is, it can be considered as a lumped constant. It therefore made sense to stipulate the load capacity.

new logic series

The dominant logic has shifted from bipolar to CMOS. The CMOS input current is almost negligible compared to the output drive capability, so the specification itself is gone. Therefore, the concept of fan-in and fan-out has also disappeared.

The rise time of the output has also become 0.2 to 0.3 ns as the process has become finer, and most of the wiring must be considered as a distributed constant (see "Boundary Line between Distributed Constant Circuits and Lumped Constant Circuits"). . In addition, it is almost no longer necessary to combine many gates to create logic. Even so, the delay time specification specifies a load capacitance of 50 pF. Since the standard logic is a kind of infrastructure, it has a role to maintain continuity with the past. I remember making such a request in the past and having it prescribed, but I can't find it now.

Misunderstanding due to large load capacity provisions

As shown in Figure 2, the waveform is blunted and delayed due to the time constant due to the large load capacitance and output resistance. Its delay time is 0.69 × CR.

Regarding the output resistance of the driver, as described in "Characteristic Impedance and Driver Driving Capacity", for example, the output resistance of a 4 mA driver is 67 Ω, and that of a 24 mA driver is about 11 Ω. The delay time when C = 50 pF is 0.7 × 50 pF × 67 Ω = 2.3 ns at 4 mA and 0.7 × 50 pF × 11 Ω = 0.38 ns at 24 mA. You need a big driver." In practice, 50 pF of load capacitance does not exist.