Quartus® Prime Development Software - Semiconductor Business -Macnica

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Product Pickup FPGA/CPLD/ASIC Altera Corporation

Overview

Quartus ^® Prime development software is available from Altera ^® Development tools for designing FPGAs, SoCs and CPLDs.
From design entry to logic verification, logic synthesis, placement and routing, timing verification, power consumption analysis, pin placement, and devices
It has the functionality required for the development flow.

Three Editions of Quartus® Prime

^Quartus® Prime design software is available in three editions: Lite, Standard, and Pro.
Each edition differs in the devices that can be used and optional features.

License Comparison Table (18.1)

●: Support, ▲: Optional (separate cost required)

	Main function	light edition (free of charge)	Standard edition (paid)	Professional edition (paid) 1 1: Standard edition with Pro edition license is also available, but the software must be installed separately Is required.
*Device support 2** 2: Supported devices differ depending on the version. See “Note:”* below the table for details	Low cost FPGA/CPLD (Cyclone ^® 10 LP, MAX ^® 10, etc.)	●	●
	General FPGA/CPLD (Cyclone ^®, MAX ^®, Arria ^®, Stratix ^® series, etc.)		●
	Latest high-end FPGAs (^Cyclone® 10 GX, ^Arria® 10, ^Stratix® 10, etc.) Arria ^® 10 is available in both Standard and Pro editions		●	● 3 3: ^Cyclone® 10 GX uses the Pro Edition, Can be used without a Pro Edition license
design entry/ planning	Multi-processor support Fast compilation using multiple processors		●	●
	Free key IP including IP base suite DDR3 controller	▲	●	●
	Platform Designer (Standard) (Formerly: Qsys) Easily connect self-made designs and IP connections using a GUI	●	●
	Platform Designer (Professional) (Formerly Qsys Pro) Fast version of Platform Designer			●
	Design Partition Planner Optimize design partitions and improve fitting efficiency		●	●
	Chip Planner Graphically set and check floor plan and placement and routing information	●	●	●
	Interface Planner (formerly BluePrint) Optimize I/O designs with complex constraints without repeated recompilation, reducing I/O design time			●
	Logical simulation	ModelSim® - Altera FPGA Starter Edition Free logic simulator	●	●	●
ModelSim®- Altera FPGA Edition Logic simulator 33% faster than Altera FPGA Starter Edition	Logical simulation	▲	▲	▲
logic synthesis	Convert logic synthesis HDL to netlist	●	●	●
Placement/wiring	Mapping fitter netlist to target FPGA/CPLD	●	●	●
	Fixed the placement and routing information of the logic lock region specific block to ensure the performance after recompilation		●	●
	Faster fitting time by splitting stages of incremental optimization fitting			●
	Reduce convergence time by initial placement considering initial placement timing			●
	Register retiming Move the register position before and after the worst path improve timing		●	●
	Hybrid placer New placement algorithm speeds up placement time		● 4 4: Arria ^® 10, Stratix ^® V, Arria ^® V : and Cyclone ^® V	●
design flow	Partial Reconfiguration Reconfigure only the inactive portion of the circuit while the FPGA is running		● 5 5: Only available for Cyclone ^® V and Stratix ^® V	●
	Rapid recompilation Shorten compile time by targeting only changed parts when recompiling		● 6 6: Available for Stratix ^® V, Arria ^® V, and Cyclone ^® V	●
	Block-based design Convenient function for team design to design blocks separately			●
timing and power verification	Timing Analyzer (formerly TimeQuest) Static timing analysis using industry standard SDC	●	●	●
	Design Space Explorer II Automatically finds different optimal compilation settings and algorithms for each design	●	●	●
	Power consumption analyzer (Formerly: PowerPlay Power Analyzer) Analyze power consumption	●	●	●
In-system debugging	Signal tap (old: SignalTap II) Waveform display of FPGA internal signals running on the actual device without using external pins	●	●	●
	Transceiver Toolkit Fast Jitter-Noise, Eye-Diagram Analysis for High-Speed Serial Links		●	●
	Advanced Link Analyzer (formerly JNEye) Analyzes jitter, noise, and eye levels on high-speed serial links		●	●
OS support	Windows/Linux (64-bit)	●	●	●
Additional software	FPGA SDK for OpenCL™: Generates kernel functions for processors from OpenCL C language (for developing accelerators using FPGAs)	●	●	●
	Altera® HLS Compiler Generates HDL optimized for Altera® FPGAs from C++	●	●	●
	DSP Builder Generate HDL for digital signal processing using MathWorks Simulink tools (Others include "DSP Builder" and "MathWorks ^®, MATLAB/Simulink ^®", "MathWorks ^® (Requires "Fixed-Point Designer")	● 4 4: Available for ^Arria® 10, ^Stratix® V, ^Arria® V and ^Cyclone® V	● 4 4: Available for Arria 10, ^Stratix® V, ^Arria® V and ^Cyclone® V	● 4 4: Available for ^Arria® 10, ^Stratix® V, ^Arria® V and ^Cyclone® V
	Nios ^® II Embedded Design Suite (EDS) Nios ^® II software development package (Nios ^® II hardware design requires a separate license)	▲	▲	▲
	SoC FPGA Embedded Development Suite (SoC EDS) SoC FPGA software development package (Both the Standard Edition and the Pro Edition are available in free and paid versions.)	●	●	●
cost		free of charge	Paid	Paid
download		download	download	download

note:

*1: You can use the Standard Edition with a Pro Edition license, but the software must be installed separately.
*2: Supported devices vary depending on the version.
・ Quartus version and supported device compatibility table can be found here
*3: ^Cyclone® 10 GX uses Pro, but can be used without a license.
*4: Available for Arria ^® 10, Stratix ^® V, Arria ^® V and Cyclone ^® V.
*5: Available for ^Cyclon® V and ^Stratix® V only.
*6: Available for ^Stratix® V, ^Arria® V, and ^Cyclone® V.

Related Information

cloud service

Each tool runs on a PC, but cloud services are also available.
There is no need to install or set up tools or libraries, and you can use a machine with the necessary specifications when you need it.

Click Here for Details

Macnica technical information site

If you have any questions about Quartus ^® Prime, please first refer to Macnica 's technical information site.
We mainly introduce frequently asked questions and information for beginners.

Altima technical information site

MACNICA Forum

User guide

Please refer to the latest Altera® getting started guides, installation guides, handbooks^, etc.
If the problem cannot be resolved on Macnica 's technical information site, please refer to here.

For more information, please visit Altera® website.

workshop

Workshops for learning how to use Quartus ^® Prime include free trials and paid training by instructors.
Free online training is available.

Course Name	cost	Overview
Quartus® Prime Introduction Trial	free of charge	I want to touch Quartus ^® Prime! I want to try it! I want to know the overview! This is a trial (introductory) course for such people. We will pick up key operations from the overall flow and explain them while conducting simple exercises.
Altera® FPGA Technical Training	Paid	This workshop is taught by an ^Altera® certified instructor and textbook. We offer a variety of courses to suit your needs.
online training	free of charge	^Altera® Online Training allows you to take various training courses anytime, anywhere.