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1

Host PC

A host PC running Linux (it is also possible to use Linux by building a virtual machine (VM) environment on a Windows PC)

In this document, we have constructed a virtual machine environment by combining Oracle® VM VirtualBox (hereafter referred to as VirtualBox) and CentOS 6.9 (hereafter referred to as CentOS 6) on Windows® 7 Professional and confirmed the operation.

Notes: 

U-Boot compilation is only supported on Linux host machines. Not supported on Windows.

Please refer to the following site for how to build a virtual machine environment.

Building a virtual machine environment with VirtualBox and CentOS 6

2

Intel® Quartus® Prime Design Software Standard Edition (or Pro Edition)

(hereafter referred to as Quartus® Prime)

A tool for developing SoC FPGA hardware.

This document uses the Quartus® Prime development software Standard Edition v18.1.

Quartus Prime Standard Edition v18.1 for Linux

Notes:

この資料で説明しているデザインファイル a10_soc_devkit_ghrd_qspi.tgz を実際にコンパイルする場合は、Quartus® Prime プロ・エディションが必要になります。

Notes:

It is necessary to install the Device data corresponding to the SoC FPGA mounted on the target board to be used.

Please refer to the following site for how to install Quartus® Prime.

Quartus® Prime & ModelSim® Installation Instructions

3

Intel® SoC FPGA Embedded Development Suite Standard Edition

(hereafter referred to as SoC EDS)

A tool for developing software for SoC FPGAs.

You can use Arm® Development Studio 5 Intel® SoC FPGA Edition (DS-5) included in SoC EDS to build and debug your application software.

This document uses SoC EDS Standard Edition v18.1.

SoC EDS Standard Edition v18.1 (Linux version)

Notes:

Intel® FPGA Download. Arm® Development Studio 5 Intel® SoC FPGA Edition (paid version) is required for debugging bare metal applications using a cable (USB-Blaster II).

Please refer to the following site for how to install SoC EDS.

How to install SoC EDS

4

Arria® 10 SoC Development Kits

This is a development kit used as a target board in the explanations in this document.

Install and use the QSPI boot flash daughter card.

Arria 10 SoC Development Kits

5

QSPI Boot Content for Arria® 10 SoC Development Kits

If you want to actually check the operation described in this document, please download the following hardware design files together with this document.

A10_SoC_DevKit_GHRD_QSPI.tgz

This document assumes that the above downloaded files are stored in /home/Student/Temp.

Notes:

The above A10_SoC_DevKit_GHRD_QSPI.tgz file was created with reference to the contents of the following pages.

GSRD tagging information

・ Arria 10 QSPI boot hardware (v17.1: a10_soc_devkit_ghrd_qspi.tar.gz)

・ Arria 10 QSPI boot precompiled binaries (v17.1: linux-socfpga-qspi-17.1-a10.tar.gz)

6

Bare metal sample application

This is the bare metal sample application used in the explanations in this document.

This bare metal application is a simple application that just displays a “Hello from Arria 10 SoC!!!” message over UART.

If you want to actually check the operation, please obtain the following application files together with this document.

ALT-HWLib-HelloWorld-Unhosted-A10-GNU.tgz

This document assumes that the above downloaded files are stored in /home/Student/Temp.

7

Terminal emulation software

A serial terminal software is required to use this sample. This article uses freeware software called "Tera Term".

Tera Term download URL

Notes:

In Tera Term, set the following for the valid COM port when connecting to the UART of the target board.

・ Baud rate 115200 bps

・ 8-bit data

・ No parity

・ 1 stop bit

・ No flow control