Microchip FPGA: What development tools do you use when developing a "ProASIC3 FPGA"?

Microchip FPGA: Other FPGA makers can use logic analyzers in their development tools, but does Microchip's Libero come with logic analyzers?

Intel: What is the purpose and range of values for the boot_scratch_cold0 to boot_scratch_cold8 registers in the System Manager group in the Intel® Stratix® 10 Hard Processor System Address Map and Register Definitions?

Intel: Error (174068): Output buffer atom "XXX" has port "YYY" connected, but does not use calibrated on-chip termination

Intel: Target selection does not appear in Run/Debug Configuration of Arm® DS

Intel: What state is each I/O pin in the Arria® 10 SoC until configuration is complete?

Microchip FPGA: How can I use older versions of IP in my Libero SoC?

Intel: On the Cyclone® V SoC FPGA development kit, when starting U-Boot v2013.01.01, the USB memory connected to the USB host cable (OTG cable) attached to the kit is not recognized. If you connect the USB Hub to the cable included in the kit and then connect the same USB memory, it will be recognized.

Microchip FPGA: regarding the pinout in the I/O Editor. It cannot be assigned to the pin assigned to "DDRIO" in I/O Editor. Actually, I want to use normal LVCMOS2.5V, but only "LVCMOS18" is listed.

Microchip FPGA: About the Libero SoC report file. Please tell me what kind of report "xxx.mindelay_repair_report.rpt" is.

Microchip FPGA: Regarding processing of unused pins in pin-compatible products by device scale in SmartFusion2/IGLOO2. For example, PKG of FG484 understood that UserI/O is upper compatible with devices from M2GL005 to M2GL090. Assuming that 209pins of UserI/O were initially set with M2GL005 as the target, how should I handle the increased "24pins" of UserI/O when changing to M2GL010?

Microchip FPGA: I installed the latest version of Libero SoC, but the library in the "Catalog" tab seems to be missing. I ran "Reload Catalog" but it didn't help. Please let me know if there is a correct procedure.

Microchip FPGA: REFCLK placement constraint rules. When using Libero SoC's I/O Editor => XCVR View tab GUI, REFCLK at the top can be used to supply clocks to all TXPLL and Lane_Quad. There are lane quads that cannot be connected depending on the REFCLK placement. Could you please give me the exact information about this constraint?

Microchip FPGAs: What is the FIT value for each device family?

Analog Devices DSP: Dual-core SHARC+ and ARM Cortex-A5 SoCs use the SC-58x series in one chip. Where can I find ARM related APIs?

Intel: Are the analog-only input pins ( ANAIN1/ ANAIN2 ) for the ADC in the MAX® 10 FPGA Hot-Socket capable?

Intel: Please tell me how to transfer files and write to Flash memory (QSPI, NAND) of HPS (Hard Processor System) via JTAG.

Intel: I am using a Cyclone® V SoC. I entered the following command in UBOOT, but the MDIO signal of EMAC0 is not output.

Intel: There is a specification of tCS min (CS# High Time (Read Instructions), CS# High Time (Program/Erase)) on the QSPI Flash side, but there was no timing regulation on the Cyclone® V SoC side. how should i fill it?

Intel: The QSPI controller timings in the Cyclone® V Device Datasheet say "Tqspi_clk", which clock is this?

Intel: In Cyclone® V SoC, I'm trying to route the HPS's SPI master device to the FPGA, but sclk is missing.

Intel: I'm trying to route the SPI master of the HPS to the FPGA in my Arria® V SoC, but I don't know how to connect each port.

Intel: In Cyclone® V SoC, how do I connect each port when routing the SPI master of the Hard Processor System (HPS) to the FPGA?

Intel: In Arria® V SoC, trying to route HPS SPI master device to FPGA but no sclk.

Intel: After writing a non-volatile AES key to an Arria® 10 SoC device and programming it into the configuration ROM using the jic file, configuration fails. What are the possible causes?

Intel: From SoC EDS Command Shell of Quartus® Prime Pro Edition ver.19.3, Eclipse can be started normally, but bsp-editor cannot be started.

Intel: I would like to access the Cyclone® V SoC with spim0 of the SPI Master Module. Please give me a specific example of read/write commands in u-boot

Intel: Regarding the Cyclone® V SoC Address Map, will 0x0000_0000 to 0x1000_0000 be remapped from 0x0000_00000 to SDRAM space after PREBOOT in BOOT ROM+ON CHIP RAM at startup and then remapped at UBOOT startup?

Intel: Uses DDR memory controllers from the Hard Processor System (HPS). Which setting is reflected in the DDR memory mode register?

Intel: When reading/writing registers implemented in the FPGA part on a system running Linux, use the ALT_WRITE_WORD / ALT_READ_WORD API functions described in socal.h of SoC EDS. Can you do it?