* Manufacturer documents are updated from time to time and the contents may change. Please always check and comply with the latest manufacturer documents.


Please refer to the following documents:
Please note that whether or not the power-up and power-down sequences are required varies depending on the two cases below.
[1] I/O glitches during power-up/power-down can be tolerated.
[2] I/O glitches during power-up/power-down cannot be tolerated.


PolarFire

Documentation > User Guides tab > PolarFire FPGA Board Design User Guide
In the 1.2 I/O Glitch section,
It says "There are three types of glitch that can occur:" and describes the three types of glitches and how to deal with them, so please refer to them as necessary.
As "To mitigate the post functional state glitch, follow the recommendations in the following table."
There are tables: Table 1-11. Power Sequencing (For GPIO) and Table 1-12. Power Sequencing (For HSIO).
https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/polarfire-fpgas/polarfire-mid-range-fpgas#Documentation

Related: Can VDD18 and VDDI (of 1.8V) of PolarFire be connected to the same regulator
        https://microchip.my.site.com/s/article/Can-VDD18-and-VDDI--of-1-8V--of-PolarFire-be-connected-to-the-same-regulator

Also, please observe the monotonic increase and ramp time of the power supply.
Documentation > Data Sheets tab > PolarFire® FPGA Datasheet
4.2.2.1 Power Supply Ramp Times Item
Quote: "All supplies must rise and fall monotonically."
https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/polarfire-fpgas/polarfire-mid-range-fpgas#Documentation


IGLOO2, SmartFusion2

・Documentation > Data Sheets tab > IGLOO® 2 FPGA and SmartFusion® 2 SoC FPGA Datasheet
Observe monotonic increase.
Quote: "Note: All power supply ramps must be strictly monotonic, without plateaus."
   https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas#Documentation

・AN4153: SmartFusion 2 and IGLOO 2 FPGA Board and Layout Design Guidelines

　https://www.microchip.com/en-us/application-notes/an4153
Online documentation: https://onlinedocs.microchip.com/oxy/GUID-2952C8AA-A592-489E-8058-3FD06065EDDB-en-US-7/index.html
Documentation > Application Notes Tab > AN4153: Board and Layout Design Guidelines for SmartFusion 2 SoC and IGLOO 2 FPGAs
   https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas#Documentation

[1.1.2 Power Supply Sequencing]

Observe monotonic increase and time.
Quote: "The power-on reset circuitry in SmartFusion2/IGLOO2 devices require the VDD and VPP supplies to ramp monotonically from 0V to the minimum recommended operating voltage within a predefined time."

There are no sequence requirements for VDD and VPP.
Quote "There is no sequencing requirement on VDD and VPP."

Please observe the ramp times defined in Libero SoC.
Quote: "Four ramp rate options are available during design generation: 50 µs, 1 ms, 10 ms, and 100 ms. Each selection represents the maximum ramp rate to apply to VDD and VPP. The ramp rates can be configured by using the Libero software."

VDD, SERDES_VDD, and SERDES_VDDAIO should use the same regulator and ramp up and down simultaneously.
Quote: "The SERDES_VDD pins are shorted to VDD on silicon die; therefore, Microchip recommends using the same regulator to power up the VDD, SERDES_VDD and SERDES_VDDAIO pins. These three voltage supplies must be powered at the same voltage and must be ramped up and ramped down at the same time."

[1.2.1 I/O Glitch During Power-Up, 1.2.2 I/O Glitch During Power-Down items]
Quote: "I/O Glitches can occur in some power-up sequences, and they can be ignored if good design practices are used.
To mitigate the I/O glitch:”
This describes what to do if I/O glitches cannot be tolerated, such as:

・Documentation > Application Notes tab > AC396: SmartFusion2 and IGLOO2 in Hot Swapping and Cold Sparing Application Note
Citation "SmartFusion2/IGLOO2 devices do not require power-up and power-down sequencing and have extremely low power-up inrush current in any power-up sequence."
   https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas#Documentation