Cyclone V FPGA Family Lineup - Semiconductor Business -Macnica

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Product Pickup FPGA/CPLD/ASIC Intel® Programmable Solutions Group (now Altera Corporation)

Introducing the Intel® Cyclone® V FPGA family lineup.

Cyclone V Family Type

The Cyclone V family consists of the following six products.

FPGA

	Cyclone VE (logic only)
	Cyclone V GX with 3.125 Gbps transceiver
	Cyclone V GT (with 5.0 Gbps transceiver)

SoC FPGAs

	Cyclone V SE SoC FPGA with ARM®-based Hard Processor System (HPS)
	Cyclone V SX SoC FPGA with ARM-based HPS and 3.125 Gbps transceiver
	Cyclone V ST SoC FPGA with ARM-based HPS and 5.0 Gbps transceiver

Table 1. Cyclone VE FPGA Family Overview

device	5CEA2	5CEA4	5CEA5	5CEA7	5CEA9
Equivalent logic element (LE) count	25,000	48,000	76,500	149,500	301,000
Number of M10K memory blocks	170	270	380	650	1,160
M10K Memory (Kb)	1,700	2,700	3,800	6,500	11,600
Memory logic array block (MLAB) (Kb)	196	270	440	836	1,717
18 x 19 bit multiplier number	50	144	248	312	684
Variable Precision DSP Block (1)	25	72	124	156	342
Number of PLLs	4	4	4	4	4
Maximum User I/O Pins	304	304	368	480	448
memory controller	1	1	2	2	2

note:

1. The DSP block contains three 9 x 9 multipliers, two 18 x 19 multipliers and one 27 x 27 multiplier. Other modes are also supported.

Table 2. Cyclone VE Device Packages and Maximum User I/O Pins

device/ package (mm x mm)	F256		U484		F484		F672		F896
	1.0 mm 17x17		0.8mm 19x19		1.0 mm 23x23		1.0mm 25x25		1.0 mm 31x31
	I/O	XVCR	I/O	XVCR	I/O	XVCR	I/O	XVCR	I/O	XVCR
5CEA2	144	-	304	-	304	-	-	-	-	-
5CEA4	144	-	304	-	304	-	-	-	-	-
5CEA5	-	-	260	-	240	-	368	-	-	-
5CEA7	-	-	-	-	240	-	336	-	480	-
5CEA9	-	-	-	-	-	-	336	-	448	-

note:

1. Gray area supports vertical package migration.

Table 3. Cyclone V GX FPGA Family Overview

device	5CGXC3	5CGXC4	5CGXC5	5CGXC7	5CGXC9
Equivalent logic element (LE) count	31,000	50,000	76,500	149,500	301,000
Number of M10K memory blocks	140	250	380	650	1,160
M10K Memory (Kb)	1,400	2,500	3,800	6,500	11,600
MLABs (Kb)	147	295	440	836	1,717
18 x 19 bit multiplier number	84	140	248	312	684
Variable precision DSP block	42	70	124	156	342
Number of PCI Express® hard IP blocks	1	2	2	2	2
Number of PLLs	4	6	6	7	8
Maximum User I/O Pins	224	368	368	480	560
memory controller	1	2	2	2	2

Table 4. Cyclone V GX Device Packages and Maximum User I/O Pins

device/ package (mm x mm)	F256		F324		U484		F484		F672		F896		F1152
	1.0 mm 17x17		1.0mm 19x19		0.8mm 19x19		1.0 mm 23x23		1.0mm 25x25		1.0 mm 31x31		1.0mm 35x35
	I/O	XVCR	I/O	XVCR	I/O	XVCR	I/O	XVCR	I/O	XVCR	I/O	XVCR	I/O	XVCR
5CGXC3	96	3	112	3	224	3	224	3	-	-	-	-	-	-
5CGXC4	-	-	128	3	240	6	240	6	368	6	-	-	-	-
5CGXC5	-	-	128	3	240	6	240	6	368	6	-	-	-	-
5CGXC7	-	-	-	-	240	6	240	6	336	9	480	9	-	-
5CGXC9	-	-	-	-	-	-	-	-	336	9	448	12	560	12

note:

1. Gray area supports vertical package migration.

Table 5. Cyclone V GT FPGA Family Overview

device	5CGTD5	5CGTD7	5CGTD9
Number of logic elements (LE)	76,500	149,500	301,000
Number of M10K memory blocks	380	650	1,160
M10K Memory (Kb)	3,800	6,500	11,600
MLABs (Kb)	440	836	1,717
18 x 19 bit multiplier number	248	312	684
Variable precision DSP block	124	156	342
Number of PCI Express hard IP blocks	2	2	2
Number of PLLs	6	7	8
Maximum User I/O Pins	368	480	560
memory controller	2	2	2

Table 6. Cyclone V GT Device Packages and Maximum User I/O Pins

device/ package (mm x mm)	U484		F484		F672		F896		F1152
	1.0mm 19x19		1.0 mm 23x23		1.0mm 25x25		1.0 mm 31x31		1.0mm 35x35
	I/O	XVCR	I/O	XVCR	I/O	XVCR	I/O	XVCR	I/O	XVCR
5CGTD5	240	6	240	6	368	6	-	-	-	-
5CGTD7	240	6	240	6	336	9	480	9	-	-
5CGTD9	-	-	-	-	336	9	448	12	560	12

note:

1. Gray area supports vertical package migration.

Table 7. Cyclone V SE SoC FPGA Family Overview

device	5CSEA2	5CSEA4	5CSEA5	5CSEA6
Equivalent logic element (LE) count	25,000	40,000	85,000	110,000
Adaptive Logic Module (ALM)	9,434	15,094	32,075	41,509
Number of M10K memory blocks	140	224	397	514
M10K Memory (Kb)	1,400	2,240	3,972	5,140
MLABs (Kb)	138	220	480	621
18 x 19 bit multiplier number	72	116	174	224
Variable Precision DSP Block(1)	36	58	87	112
Number of FPGA PLLs	4	5	6	6
hard processor system (HPS) Number of PLLs	3	3	3	3
Maximum FPGA User I/O Pins	124	124	288	288
Maximum number of HPS I/Os	188	188	188	188
FPGA hard memory controller	-	1	1	1
HPS hard memory controller	1	1	1	1
Processor core (ARM ® Cortex™-A9)	Single/dual	Single/dual	Single/dual	Single/dual

note:

1. The DSP block contains three 9 x 9 multipliers, two 18 x 19 multipliers and one 27 x 27 multiplier. Other modes are also supported.

Table 8. Cyclone V SE SoC FPGA Device Packages and Maximum User I/O Pins

Device/Package (mm x mm)	U484		U672		F896
	0.8mm 19x19		0.8mm 23x23		1.0 mm 31x31
	FPGA I/O	HPS I/O	FPGA I/O	HPS I/O	FPGA I/O	HPS I/O
5CSEA2	66	161	124	188	-	-
5CSEA4	66	161	124	188	-	-
5CSEA5	66	161	124	188	288	188
5CSEA6	66	161	124	188	288	188

Table 9. Cyclone V SX SoC FPGA Family Overview

device	5CSXC4	5CSXC5	5CSXC6
Equivalent logic element (LE) count	40,000	85,000	110,000
Adaptive Logic Module (ALM)	15,094	32,075	41,509
Number of M10K memory blocks	224	397	514
M10K Memory (Kb)	2,240	3,972	5,140
MLABs (Kb)	220	480	621
18 x 19 bit multiplier number	116	174	224
Variable precision DSP block	58	87	112
Maximum number of transceivers	6	9	9
Number of PCI Express hard IP blocks	2	2	2
Number of FPGA PLLs	5	6	6
Number of HPS PLLs	3	3	3
Maximum FPGA User I/O Pins	124	288	288
Maximum HPS I/Os	188	188	188
FPGA hard memory controller	1	1	1
HPS hard memory controller	1	1	1
Processor core (ARM Cortex-A9)	dual	dual	dual

Table 10. Cyclone V SX SoC FPGA Device Packages and Maximum User I/O Pins

Device/Package (mm x mm)	U672			F896
	0.8mm 23x23			1.0 mm 31x31
	FPGA I/O	HPS I/O	XCVR	FPGA I/O	HPS I/O	XCVR
5CSXC4	124	188	6	-	-	-
5CSXC5	124	188	6	288	188	9
5CSXC6	124	188	6	288	188	9

Table 11. Cyclone V ST SoC FPGA Family Overview

device	5CSTD5	5CSTD6
Equivalent logic element (LE) count	85,000	110,000
Adaptive Logic Module (ALM)	32,075	41,509
Number of M10K memory blocks	397	514
M10K Memory (Kb)	3,972	5,140
MLABs (Kb)	480	621
18 x 19 bit multiplier number	174	224
Variable precision DSP block	87	112
Maximum number of transceivers	9	9
Number of PCI Express hard IP blocks	2	2
Number of FPGA PLLs	6	6
Number of HPS PLLs	3	3
Maximum FPGA User I/O Pins	288	288
Maximum HPS I/Os	188	188
FPGA hard memory controller	1	1
HPS hard memory controller	1	1
Processor core (ARM Cortex-A9)	dual	dual

Table 12. Cyclone V ST SoC FPGA Device Packages and Maximum User I/O Pins

Device/Package (mm x mm)	F896
	1.0 mm 31x31
	FPGA I/O	HPS I/O	XCVR
5CSTD5	288	188	9
5CSTD6	288	188	9

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