Altera® FPGA's Nios® II Processor - Semiconductor Business -Macnica

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Design FPGA/CPLD/ASIC Microcontrollers, Processors, and DSPs Altera Corporation

The ^Nios® II processor is an Altera® A 32-bit embedded processor architecture designed for FPGAs.

Nios ^® II is suitable for a wide range of embedded computer applications from DSP to system control.

This page introduces the information and content necessary for development for Nios ^® II users.

Click the button below to access the information you want to know.

*Nios ^® II Embedded Design Suite (Nios ^® II EDS)
*Nios ^® II Software Build Tools for Eclipse (Nios ^® II SBT)

what's new

2023.06 [Updated] A new article has been added to the Nios® II summary page.

Nios^® II コンテンツ集です
Nios^® II に関する弊社情報をまとめたポータルサイトです。Nios^® II 開発に役立つ各種コンテンツがそろっています。Nios^® II Boot 方法や Nios^® II SBT ノウハウ FAQ などもご用意しています。

Nios® II Altera® User Guide Collection
Find all the Nios ^® II related user guides.

Nios^® II に関する FAQ
弊社でご用意している FAQ 集です。

The latest version requires environment construction
From Ver 19.1_Standard, Ver19.2_Pro, it is necessary to enable WSL and install Eclipse. It describes how to set up your environment.

Nios ^® II SBT Development Methodology
A concise summary of the items necessary for Nios ^® II software development, divided into three parts.

Nios ^® II Lab Content
Exercise content is available for those who are using Nios ^® II for the first time. You can learn how to create a Nios ^® II System, how to operate a Nios ^® II SBT, and even how to boot a Nios ^® II.

For those who want to know how to boot
There are many boot methods for Nios ^® II, and this content summarizes the boot methods. There is a method to boot from Configuration ROM and a method to boot from On Chip RAM.

For those who want to access Flash ROM
Contents that summarizes Flash Controller for connecting Nios ^® II and Flash ROM. Depending on the Boot configuration, a Flash Controller may be required, so please read along with the Boot method.

For those who want to do a Memory Test
Use this to check if the Flash Controller and Nios ^® II are connected. It can be used with Flash Controllers that support the Nios ^® II HAL API.

For those looking for sample designs
Altera® Design Store page.
This page allows you to search for Design Examples by setting criteria (designs are free to download).

Official Altera® Knowledge Base
This site provides tips and troubleshooting tips for using Altera® FPGA products.

For those looking for official content
This is the official Altera® ^Nios® II development support page. It compiles resources and content to help you with your development.

1. What is Nios® II?

A 32-bit RISC soft-core processor that can be installed in all Altera® FPGAs.

Since it is a soft core, the system designer selects and generates the desired Nios ^® II core (Nios ^® II/f [Fast], Nios ^® II/e [Economy]), and the size of the cache and the implementation of the arithmetic unit In a normal microcomputer, you can also set fixed values.

* Nios ^® II/e [Economy] is available free of charge.

Nios® II processor configuration example

In addition, since the peripherals are selected by the designers themselves, the address map can be freely determined.

Add peripheral and address setting example

About the Nios® II Generation

Nios ^® II has the following two generations.

- Nios ^® II Classic processor (or Nios ^® II Gen 1 processor)

- Nios ^® II processor (or Nios ^® II Gen 2 processor)

Development of the Nios ^® II Classic processor feature ended with the Quartus ^® II 14.0 release, and the Nios ^® II Gen2 processor is only available with the Quartus ^® II 14.1 release and later.

Classic processors will continue to be supported, but the manufacturer recommends using Gen2 cores in future designs.

We also have documentation for Classic processors on our website, so please use the documentation and samples that are appropriate for your Nios ^® II processor.

[Reference] Nios ^® II Gen2 Processor Reference Guide

⚠ Note:

* Basically, Nios ^® II Gen 2 is upwardly compatible with Nios ^® II Classic, but please note that there are differences in some functions.
* In this page, we mainly post the information of Nios ^® II Gen 2 processor.

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2. Necessary Tools and Development Flow for Nios® II Development

The Nios ^® II development flow can be divided into the “hardware development process” and the “software development process”.

During the hardware development process, ^Nios® II itself and peripheral configurations are performed using Platform Designer (formerly Qsys), which is included in the Altera® ^Quartus® Prime design software.

The software development process is done with the popular Eclipse-based Nios ^® II SBT included in the Nios ^® II EDS.

Hardware development process (Platform Designer)

• Nios ^® II hardware is designed using Platform Designer.

・Q uartus ^®Nios using components from the Prime package ^®II Configure and generate the system.

After you finish generating your hardware configuration in Platform Designer, Quartus ^®Primetakes care of the synthesis, placement and connectivity implementation of the entire target FPGA system.

• A GUI for ^{configuration}allows the user to select the detailed implementation of Nios ® II, including peripherals and I/O blocks such as timers, memory controllers andserial interfaces.

[Reference] Quartus ^® Prime Platform Designer (formerly Qsys) system integration tool

Software development process (Nios® II SBT)

・ Nios^® II EDS は、Nios^® II ソフトウェア・デザイン用の包括的な開発パッケージです。

• The Nios^® II EDS includesnot only development tools, but also software, device drivers, bare-metal hardware abstraction layer (HAL) libraries, and more.

・Nios^®Nios, included in II EDS^®II SBT is all Nios^®II An integrated environment for software development work.

[Reference] Software development using Nios ^® II SBT

Example of software development using Nios® II SBT

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3. Nios® II Partner Links

Nios ^® II processor ecosystem

Embedded Operating System (OS)

The table below lists the operating systems (OS) that support Nios ^® II.

operating system	vendor
^eCosPro®	eCos Centric
^eCos®	Zylin
embOS	Segger
^Euros®	Euros
FreeRTOS™	FreeRTOS
Linux™	RocketBoards.org (open source community)
µC/OS-II™ (Evaluation version included in Nios ^® II EDS, licensed separately)	Micrium (Provided by Japanese distributor: Techno Logic)
TargetOS™	Blank Microsystems
^ThreadX®	Express Logic (Provided by Japanese distributor: Grape System)
Toppers	Toppers
µC Linux	Altera® FPGA Wiki (open source community)
^µC3®	e force
Zephyr™	Zephyr (Linux™ Foundation project)

Table 3-1: Operating Systems That Support Nios ^® II

Middleware and graphics libraries

The table below lists the middleware and graphics libraries that support Nios ^® II.

company name	OS support	network stack	file system	Graphics ·Library	USB stack	Others
eCos Centric	^eCosPro®	Built-in	Built-in	-----	-----	-----
Express Logic (Provided by Japanese distributor: Grape System)	^ThreadX®	NetX™	^FileX®	GUIX	USBX	-----
Inter Niche	Any	NicheStack TCP/IP Network Stack – Nios ^® II edition (Nios ^® II included in EDS, but licensed separately)	-----	-----	-----	-----
Mentor Graphics	^Nucleus®	Nucleus Networking	Nucleus Storage	Nucleus UI	Nucleus USB	-----
Micrium (Provided by Japanese distributor: Techno Logic)	µC/OS-II™	Micrium TCP/IP	µC/OS-FS	µC/OS GUI	Micrium USB	µC/OS CAN
Micro Digital	Any	-----	-----	-----	-----	^GoFast® Floating Point Library
Altera® FPGA	Any	Design Store	read-only zip file system (included in Nios ^® II EDS)	Design Store	-----	-----
TES	Any	-----	-----	DAVE 2D & 3D	-----	-----
uGFX	Any	-----	-----	uGFX	-----	-----

Table 3-2: Middleware and graphics libraries supporting Nios ^® II

software development tools

The table below lists the software development tools that support Nios ^® II.

supply vendor	product	detail
Mentor Embedded	Sourcery CodeBench™	GNU toolchain support for Nios ^® II processor-based embedded Linux™.
Altium	Tasking* Toolset	Optimize the C compiler, assembler, linker, and locator.
MIPS (formerly FS2)	System Navigator	The System Navigator probe for Nios ^® II processors supports the special features and peripherals of the Nios ^® II core embedded in Altera® FPGAs.
RocketBoard.org (open source community)	Linux™ toolchain	A Linux™ toolchain provided by RocketBoard.org, an open source community.
Altera® FPGA Wiki (open source community)	µCLinux toolchain	This is a µLinux toolchain provided by the Altera® FPGA Wiki (open source community).

TABLE 3-3: SOFTWARE DEVELOPMENT TOOLS SUPPORTING NIOS ^® II

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4. Published Sites and Sample Designs

The table below provides links to Nios ^® II system related information portal pages.

Publisher	Name	Overview
Altera® FPGAs and Programmable Devices	Nios ^® II Processors Support (English / Japanese)	Altera® ^Nios® II related materials page
	^Nios® II Embedded Design Suite (English / Japanese)	Nios ^® II EDS page
	Altera® FPGA & SoC / Documents / Document List Page	Altera® FPGA & SoC Product Literature List Page
	design example	Altera® design example page. Click on "Embedded Processors" in the categories on this page to view Nios ^® II design examples. However, many of the samples correspond to older versions of ^Quartus® Prime (^Quartus® II) (ver.7.2 to ver.13.1). Designs targeting the Altera® MAX 10 FPGA family and its development kits are available in the Design Store.
	Design Store	Altera® Design Store page. This page allows you to search for Design Examples by setting criteria (designs are free to download).
	Knowledge Base	This site provides tips and troubleshooting tips for using Altera® FPGA products.
Macnica Semiconductor Business Top Page	Macnica website Technical information: Nios ^® II	Nios ^® II related technical information page on Macnica website
Macnica Semiconductor Business Top Page	Macnica website FAQ: Nios ^® II	Nios ^® II related FAQ page on Macnica website
Macnica, Inc. Altera® FPGA Technology Website	Ultima Company Technical Support Technical Content: Nios® II	Ultima Company Technical Support Nios ^® II Related Technical Content Page