explanation

As the speed of the external memory interface (EMIF) increases, the reduction of the data valid window (effective window of data) and the deterioration of signal quality are raised as issues.

As the amount of time spent on verification and debugging to meet the required specifications tends to increase, it is important to design device boards according to appropriate procedures and to implement means for debugging in advance at the design stage.

This document presents the design flow and debug flow, and aims to solve problems quickly by preventing bugs from entering and implementing the mechanism necessary for debugging by designing in an appropriate procedure. it was created.

Target device: Arria® 10
Target memory topologies: DDR4, DDR3

<Contents>

Introduction
Design flow
Debug Flow
Appendix
Checklist
How to check DDR4 parameters
How to create Example Designs
Using the EMIF ToolKit

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