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This document provides a user-friendly explanation for first-time users of Questa* - Altera® FPGA Edition, which is offered to Altera® FPGA users.
For information on FPGA/CPLD development flows, please refer to this link.
explanation
This document will be useful during the "4. Logic Simulation" phase of FPGA/CPLD development.
This document demonstrates how to use Questa* - Altera® FPGA Edition to simulate and verify the operation of logic circuits.
To perform logic simulation (RTL simulation) before logic synthesis, use a simulator for hardware description languages (HDL), such as Questa* - Altera® FPGA Edition.
Document
ModelSim-Altera RTL Simulation Methods
Tool version: Documentation for Ver.15.1 (ModelSim-Altera 10.4b)
* Although the document title is still for ModelSim, the basic procedure is the same for Questa.