FPGA/CPLD design is all about synchronous design!

This is not limited to Intel's FPGAs and CPLDs, but is common to all FPGA/CPLD manufacturers.

To understand it, let's first understand the advantages and disadvantages of synchronous and asynchronous.

What is a synchronous circuit

"A circuit system that operates in synchronization with the same edge of the same clock".

Therefore, even if they are the same clock, they are not regarded as the same clock if they use opposite phase edges.

Also, basically single clock synchronization is preferable. Sending and receiving signals between different clocks is an asynchronous circuit, and appropriate processing for asynchronous inputs is required.

Advantages of synchronous circuits	Disadvantages of synchronous circuits
Easy to time Configurable glitch-free system Capable of high-speed operation easy to debug	high power consumption Circuit size tends to be large

 

A design example of synchronous design is shown in VHDL description and VerilogHDL description.

VHDL

Verilog HDL

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity s_counter is port ( clk : in std_logic; enable : in std_logic; q : out std_logic ); end s_counter; architecture sync_pld of s_counter is begin process (clk) variable cnt : std_logic_vector(2 downto 0); begin if enable = '0' then cnt := cnt; elsif (rising_edge(clk)) then cnt := cnt + 1; end if; q <= cnt(2); end process; end sync_pld;

module s_counter (clk, enable, q); input clk, enable; output q; reg[2:0]cnt; always @(posedge clk) if (enable) cnt = cnt+1; else cnt = cnt; assign q = cnt[2]; end module

What is an asynchronous circuit

It means "a circuit system that does not operate in synchronization with the same edge of the same clock".

Therefore, even if the clock is the same, the circuit that operates with different clock edges is an asynchronous circuit.

Ripple clocks are a prime example. In addition, reusing the internally divided output also becomes an asynchronous clock with respect to the source clock.

Advantages of asynchronous circuits	Disadvantages of asynchronous circuits
Small circuit scale low power consumption	it's hard to get the timing right low operating frequency Timing simulation is difficult

 

Design examples of asynchronous design are shown in VHDL description and VerilogHDL description.

VHDL

Verilog HDL

library ieee; use ieee.std_logic_1164.all; entity a_counter is port ( clk : in std_logic; enable : in std_logic; q : out std_logic ); end a_counter; architecture async_pld of a_counter is signal cnt2, cnt1, cnt0: std_logic:='0'; begin q0: process (clk) begin if (enable='0') then cnt0 <= cnt0; elsif rising_edge (clk) then cnt0 <= not cnt0; end if; end process q0; q1: process (cnt0) begin if rising_edge (cnt0) then cnt1 <= not cnt1; else cnt1 <= cnt1; end if; end process q1; q2: process (cnt1) begin if rising_edge (cnt1) then cnt2 <= not cnt2; else cnt2 <= cnt2; end if; end process q2; q <= cnt2; end async_pld;

module a_counter (clk, enable, q); input clk, enable; output q; reg cnt0, cnt1, cnt2; always @(posedge clk) begin if (enable) cnt0 = ~cnt0; else cnt0 = cnt0; end always @(posedge cnt0) cnt1 = ~cnt1; always @(posedge cnt1) cnt2 = ~cnt2; assign q = cnt2; end module

 

Design examples using anti-phase clocks are shown in VHDL description and VerilogHDL description.

VHDL

Verilog HDL

library ieee; use ieee.std_logic_1164.all; entity rev_clk is port ( clk : in std_logic; data : in std_logic; q : out std_logic ); end rev_clk; architecture rev_clk_pld of rev_clk is signal int0, int1: std_logic; begin process (clk) begin if (rising_edge(clk)) then int0 <= data; else int0 <= int0; end if; end process; process (clk) begin if (falling_edge(clk)) then int1 <= int0; else int1 <= int1; end if; end process; q <= int1; end rev_clk_pld;

module rev_clk (clk, data, q); input clk, data; output q; reg int, q; always @(posedge clk) int = data; always @(negedge clk) q = int; end module

Based on the above

Synchronous design with a single clock is the basic concept for ensuring high design quality in systems using FPGAs and CPLDs.

As FPGAs/CPLDs grow in scale, device vendors are proposing various interconnect schemes to ensure flexibility while maintaining high speed.

However, it is practically impossible to arrange the delays in all devices so that they are uniform throughout a single device.

Additionally, these delays often vary due to external factors such as voltage fluctuations, ambient temperature, and lot variations.

An asynchronous design under these conditions creates a race between clock and data signals. Occasionally, a "skipping" condition occurs where the data overtakes the clock.

To prevent this, it is necessary to perform synchronous design while maintaining the worst-case conditions recommended by Intel.

As long as you do a synchronous design, the clock skew is adjusted to the minimum inside the device, so you don't have to worry about ``dropping out''.

Therefore, the only thing to be careful about is securing the setup time and hold time of the input signal from the outside.

I would like you to be conscious of these points and build a more reliable digital logic circuit design.
This time, I explained about synchronous and asynchronous circuits, which are the basics of FPGA / CPLD design.