Category: IP (PCI-Express®)


By using the design at the following URL, you can check the operation of the design that implements the Qsys-based Avalon®-MM compatible PCI-Express core.

http://www.alterawiki.com/wiki/PCI_Express_in_Qsys_Example_Designs

At this time, we have registered designs for the following Altera evaluation boards.

Cyclone® IV GX Starter Kit
Cyclone IV GX Development Kit
Cyclone V GT Development Kit
Arria® II GX Development Kit
Arria V GX Starter Kit
Stratix® IV GX Development Kit

These designs can be customized by the user and implemented on the original board, and operation verification can be performed using software that runs on Windows® without changing the address settings inside Qsys. increase.

This software that runs on Windows determines the device series by reading the Subsystem Device ID set in the PCI-Express core of the FPGA through configuration access via the PCI-Express link at startup.

For example, a design for a Cyclone V GT device has 0x00002482 set, and if this value is set, the device series display in the GUI will show as Cyclone V. For other devices, the following values correspond.

Cyclone IV : 0x00002444
Cyclone V : 0x00002484
Arria GX : 0x00002434
Arria II GX : 0x00001434
Arria V : 0x00002474
Stratix II : 0x00002424
Stratix IV : 0x00002404
Stratix V : 0x00002464

This value can be arbitrarily set by the user from the PCI-Express core setting screen on Qsys. Note that even if this value is random, it does not affect the operation of the software.