Intel: What kind of analysis will be performed if I do not define a clock in TimeQuest Timing Analyzer?

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Intel: What kind of analysis does the TimeQuest Timing Analyzer perform if I don't define any clocks?

Quartus Prime Timing constraints/analysis

The TimeQuest Timing Analyzer applies the following constraints by default if there are no clock constraints.
derive_clocks -period 1.0
derive_pll_clocks

Therefore, if the clock is not defined, the analysis is performed assuming an input frequency of 1GHz.
Regarding the output of PLL, the output is automatically defined from the PLL setting by "derive_pll_clocks" command.

All clock constraints related to the FPGA must be entered into the .sdc file for a solid timing analysis.

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