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Intel: Implementing a flip-flop with synchronous clear is implemented in combinatorial logic. How can I use the sclr port?
Category: Tools
Tools: Quartus® Prime
Device: Cyclone® 10 LP
To force the Quartus Prime compiler to use the sclr port,
Apply the following logic options to the appropriate registers in the Assignment Editor.
Force Use of Synchronous Clear Signals = On
Enabling this option helps reduce the total number of logic cells used in the design, but
All logic cells within a LAB (Logic Array Block) share synchronous control signals, which can adversely affect fitting.
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