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Intel: I am using the PHY Lite for Parallel Interfaces Intel FPGA IP. When setting the Pin Output Delay of the Control Register from the Avalon Memory-Mapped Interface, how long does it take for the state to be reflected to the external pins of the PHY Lite IP?
Category: Memory Interface
Tools: Quartus® Prime Pro Edition
Device:-
According to the PHYLite user guide, the number of VCO clocks is about 50clk.
For exact values, please check by running RTL simulation.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_phylite.pdf#page=58
3.2.5.3. Reconfiguration Features and Register Addressing
For example, it takes approximately 50 VCO clock cycles for the output delay to change value. Perform an RTL simulation to show an accurate timing which correlates to the hardware operation.
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