Intel: When I performed an RTL simulation of a MAX® 10 FPGA ADC using ModelSim®, I tried porting a design to a different directory and performed the same task, but an error message occurred.

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Intel: I have a proven design with RTL simulation of an ADC for a MAX® 10 FPGA in ModelSim®, and I ported it to a different directory and did the same thing, but I get an error message.

IP MAXSimulation _

Category: IP (Other) / Simulation
Tools: ModelSim®
Device: MAX®10

Protected: /( Path Name )/adcblock_instance/primitive_instance/inst/<protected>/<protected>/<protected>
** Error (suppressible): (vsim-PLI-3084) nofile(38): $fscanf : Argument 1 is not a valid file descriptor.

This error occurs when the project is ported without changing the path of the file that stores the data for simulation set in the Modular ADC IP core.

For the ported project, launch the IP Parameter Editor and check the User created expected output file column for the Modular ADC IP.
If the path before porting remains, specify the data file in the path after porting again.

In addition, if you change the path, Regenerate is required.

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