Intel: For FPGAs with a 20nm process or less, even if you generate the ALTERA_FP_FUNCTIONS simulation model with Verilog specifications, the lower module at the end will be generated as a VHDL file. Is it possible to simulate with VCS?

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Intel: Even if the simulation model of ALTERA_FP_FUNCTIONS is generated with Verilog specification for FPGA with 20nm process or less, the lower module at the end is generated as a VHDL file. Can't you simulate with VCS?

Arria Quartus PrimeSimulation

Category: Simulation
Tools: Quartus® Prime
Device: Arria® 10

RTL-level simulation of the ALTERA_FP_FUNCTIONS IP (FP_FUNCTIONS Intel FPGA IP) requires a bilingual simulator.
Therefore, it is not available in VCS.
Consider using a language mixed simulator such as VCS MX.
Alternatively, ModelSim-Intel FPGA Starter Edition provided free of charge by Intel PSG is a bilingual simulator and can be used here.

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