Category: SoCs
Tools: Quartus® Prime
Device: Cyclone® V

When routing to the FPGA side, connect each port as follows.
Here is an example where SPI master and SPI slave are connected one-to-one.

.hps_0_spim0_txd           (hps_spim0_txd ),  // mosi
  .hps_0_spim0_rxd           (hps_spim0_rxd ),  // miso
  .hps_0_spim0_ss_in_n       (1'b1          ),  // ss_in_n  マルチ・マスター・システムで使用。 Motorola SPI 向けは、デフォルトで "1" にする
  .hps_0_spim0_ssi_oe_n      (1'b0          ),  // ssi_oe_n 1対1接続の場合は、常時出力。
  .hps_0_spim0_ss_0_n        (hps_spim0_ss0 ),  // ss_0_n
  .hps_0_spim0_ss_1_n        (              ),  // ss_1_n
  .hps_0_spim0_ss_2_n        (              ),  // ss_2_n
  .hps_0_spim0_ss_3_n        (              ),  // ss_3_n
  .hps_0_spim0_sclk_out_clk  (hps_spim0_sclk),  // sclk

For details on each port, refer to the "SPI Controller" chapter in the "Cyclone V Hard Processor System Technical Reference Manual".
https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html

For SPI connection, please refer to Example below.
https://www.intel.com/content/dam/altera-www/global/en_US/others/support/examples/soc/Altera-SoCFPGA-HardwareLib-SPI-CV-GNU.tar.gz