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Intel: Implemented multiple PCI-Express (PCIe) Hard IPs and Transceivers in Arria® 10 devices. Please let me know if there are any points to be aware of when starting.
Category: PCI-Express
tool:-
Device: Arria® 10
Arria® 10 devices perform Power-Up Calibration at startup, but CLKUSR and the Reference Clock (Refclk) supplied to each Transceiver must be stably supplied.
(Reference) Intel® Arria® 10 Transceiver PHY User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf
(Refer to item 7. Calibration)
Arria 10 devices use CLKUSR for transceiver calibration.
calibration process, the CLKUSR clock must be stable and free running at the start of
FPGA configuration. Also, all reference clocks driving transceiver PLLs (ATX PLL, fPLL,
CDR/CMU PLL) must be stable and free running at start of FPGA configuration.
If this content is not followed, phenomena such as Transceiver Calibration not being executed and PCIe Linkup being unable to be performed normally will occur.
Please refer to the following Knowledge Database (KDB) for information related to PCIe.
Why might Arria 10 Transceiver calibration fail?
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2016/why-doesn-t-the-gen3-stratix-v-pcie-hip-start-flow-control-initi.html
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