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Intel: I am designing a PCI-Express (PCIe) Root Port IP using a Cyclone® V SoC. Which of CfgRd0/CfgWr0 or CfgRd1/CfgWr1 should be used for the TLP issued by accessing the Root Port's own Configuration Register...
PCI Express
Category: PCI-Express
tool:-
Device: Cyclone® V
First, PCIe has the following types of Configuration Space Registers.
- Root Port: Type 1 Configuration Space Registers
- Endpoint: Type 0 Configuration Space Registers
The TLPs used to access the Root Port Type 1 Configuration Register are CfgRd0 (Configuration Read Type 0) and CfgWr0 (Configuration Write Type 0).
When accessing the Type 0 Configuration Register on the Endpoint side, issue CfgRd1 (Configuration Read Type 1) and CfgWr1 (Configuration Write Type 1).
(For details, please refer to the standard document.)
Therefore, first issue CfgRd0 and CfgWr0 to set the Root Port itself, then issue CfgRd1 and CfgWr1 to set the Endpoint side.
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