Intel: I am using Quartus® Prime Standard Edition v17.1. When LVDS is configured with External PLL, when you look at the timing report for the loadena clock constrained by derive_pll_clocks, the value differs from the PLL setting.

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Intel: I am using Quartus® Prime Standard Edition v17.1. When I configure LVDS with External PLL, the loadena clock constrained by derive_pll_clocks shows a different value than the PLL setting when I look at the timing report.

Category: Timing Constraint/Analysis
Tools: Quartus® Prime
Device: Arria® 10

This is a confirmed issue in Quartus® Prime Standard Edition v17.1.
As a workaround, add an SDC timing constraint on the create_generated_clock for loadena.

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