Category: External memory interface
Tools: Quartus® Prime
Device: Arria® 10


When verifying the memory on the HPS side, create a memory IP on the FPGA side and set the pin assignment for the memory on the HPS side.
If your memory is DDR4, you can use the Emif tool kit by enabling the setting.

For DDR3, you need to work on your HDL and settings.
To use the EMIF ToolKit with DDR3 on Arria 10 SoC devices, you need to:

1. Generate Example Design

• In the Example Design tab, select Arria 10 GX DDR3 HiLo for Target Development Kit
• Select the same in the preset and press Apply to apply the setting
• Select Add EMIF Debug Interface in the Diagnostics tab
• Match memory parameters such as data width and board skew
• Generate Example Design to create Example Design

2. Editing the Example Design project

• Edit the QSF file to match your pinout
• Copy the signals in the ed_synth_top.sv file from the signals in the ed_synth.v file (ed_synth_top.sv has GX preset settings, so match the parameters to the signals you want to use)
• Check Device Settings in QSF File and Compile