Narrow down by specifying conditions
There are currently 4292 hits.
Intel: If PHY IP Core for PCI Express (PIPE) and Reconfig Controller are connected, is Reconfig Interface fixed at 0 or Open?
Category: PCI Express®
Tools: Quartus® Prime / Quartus® II
Device: Cyclone® V
It is necessary to connect reconfig_to_xcvr and reconfig_from_xcvr of PIPE IP to reconfig_to_xcvr and reconfig_from_xcvr of Transceiver Reconfiguration Controller IP.
Also, as long as a free-running 75-125 MHz clock is supplied to the mgmt_clk_clk clock, there is no problem in fixing the other reconfig_mgmt*** signals to ALL 0.
Experienced FAE
Free consultation is available.
From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.