After enabling ECC for the SDRAM controller in a Hard Processor System (HPS), why do I keep getting errors when injecting errors using the ctrlcfg register? Also, please tell me how to read the erraddr register, which indicates the address where the SDRAM ECC error occurred.

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After enabling ECC for the SDRAM controller in the Hard Processor System (HPS), why is the error repeatedly detected when injecting errors using the ctrlcfg register? Also, how do I interpret the erraddr register, which indicates the address where the SDRAM ECC error occurred?

SoC FPGAs

Category: SoCs
Tool: SoC EDS
Device: Cyclone® V

If an ECC error is forcibly generated, the ECC information remains corrupted until write access is issued to the corresponding address, and the error is detected again when read access occurs to the same address.
Therefore, perform write access before issuing read access.

The address displayed in the erraddr register is based on the address with 64bit (8byte) as one word.
Therefore, it must be multiplied by 8 to convert to an address (byte address) as seen from the ARM* CPU.

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