Category: Programming/Configuration
Tools: Quartus® Prime / Quartus II
Device: Arria® 10


Theoretically there is no difference.
This is because the fastest interface between the PR controller IP and the PR block is clk = 100MHz and data width = 32, and in both cases the controller configuration must be designed to satisfy the above conditions.

However, this does not mean that you must use the Clock Crossing Bridge.
Qsys automatically inserts a Clock Crossing Adapter to absorb clock domain differences.
The Clock Crossing Adapter adjusts through a handshake protocol or FIFO, so this can be an effective approach if you need to consider simple design configurations or latency.

Please refer to the following document for details.
https://www.altera.co.jp/en_JP/pdfs/literature/hb/qts/qsys_optimize_e.pdf
(Please search with keywords such as clock crossing.)