When compiling a design that uses the FIR Compiler II MegaCore function, the compilation fails due to insufficient DSP block resources in the target FPGA. Please let me know if there is a way to reduce resources.
Category: DSP
Tools: Quartus® Prime / Quartus II
device:-
Although it depends on the design specifications, the following countermeasures are available.
- Method 1
Change the sampling clock of the filter to a slower speed than the operating clock
For example, if you set both the operating clock and sampling clock to 100MHz and encounter a fitting error:
Clock Rate: 100
Input Sample Rate (MSPS): 100
In this case, changing the sampling clock to 200 kHz as follows will eliminate the fitting error.
Clock Rate: 100
Input Sample Rate (MSPS): 0.2
The filter's sampling clock is slow enough compared to the operating clock to allow sharing of a minimal number of DSP blocks in a time division manner.
- Method 2
Change to Symmetrical
If the filter coefficients are symmetrical, changing the pull-down menu in the Symmetrical column of the Coefficients tab to Symmetrical halves the number of taps and, as a result, halves the number of DSP blocks used.
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