SLVS-EC v3.2 Rx IP - Semiconductor Business -Macnica

The SLVS-EC v3.2 interface for next-generation CMOS image sensors is implemented using FPGA.

Overview

The SLVS-EC v3.2 Rx IP is an interface IP core that operates on Altera® FPGAs. This IP enables the rapid and easy implementation of products compliant with the latest SLVS-EC v3.2 standard. An evaluation kit is also available for early adoption.

Realizing reception function from SLVS-EC interface using Altera® FPGA
Compliant with the latest SLVS-EC Specification Version 3.2.
Supports powerful De-Skew function. Allows you to design boards without having to worry about skew between lanes.
An evaluation kit is available for speedy evaluation of actual equipment.

Example of system configuration using this IP

SLVS-EC Standard Overview

SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock) is an interface standard for high-resolution, high-speed image sensors developed by Sony Semiconductor Solutions Corporation.
The SLVS-EC standard is being standardized by the Japan Industrial Imaging Association (JIIA).

SLVS-EC interface connection to Sensor

Features

Compatible with SLVS-EC Specification Versions 1.2/2.0/3.0/3.1 and the latest 3.2.
Realizes various functions defined in the SLVS-EC Link layer
- 32 or 64 pixel selectable output interface
- Supports 8, 10, 12, 14, 16 bits per pixel
In addition to ANSI 8b10b and GCC (Gigabit Channel Coding), it also supports 64b66b, which was added in SLVS-EC v3.2.
Supports error correction function using ECC (Error Correction Code)
Supports Byte to Pixel conversion in 1, 2, 4, 6, and 8 lane configurations
Includes header parsing and payload error detection
Unnecessary functions can be removed using compile options.